- 07 Jan, 2014 40 commits
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Archit Taneja authored
Use the csc library functions to configure the CSC block in VPE. Some changes are required in try_fmt to handle the pix->colorspace parameter more correctly. Previously, we copied the source queue colorspace to the destination queue colorspace as we didn't support RGB formats. Now, we configure pix->colorspace based on the color format set(and the height of the image if it's a YUV format). Add basic RGB color formats to the list of supported vpe formats. If the destination format is RGB colorspace, we also need to use the RGB output port instead of the Luma and Chroma output ports. This requires configuring the output data descriptors differently. Also, make the default colorspace V4L2_COLORSPACE_SMPTE170M as that resembles the Standard Definition colorspace more closely. Signed-off-by:
Archit Taneja <archit@ti.com> Signed-off-by:
Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by:
Mauro Carvalho Chehab <m.chehab@samsung.com>
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Archit Taneja authored
The CSC block can be used for color space conversion between YUV and RGB formats. It is configurable via a programmable set of coefficients. Add functionality to choose the appropriate CSC coefficients and program them in the CSC registers. We take the source and destination colorspace formats as the arguments, and choose the coefficient table accordingly. YUV to RGB coefficients are provided for standard and high definition colorspaces. The coefficients can also be limited or full range. For now, only full range coefficients are chosen. We would need some sort of control ioctl for the user to specify the range needed. Not sure if there is a generic control ioctl for this already? Signed-off-by:
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Archit Taneja authored
VPE and VIP IPs in DAR7x contain a color space converter(CSC) sub block. Create a library which will perform CSC related configurations and hold CSC register definitions. The functions provided by this library will be called by the vpe and vip drivers using a csc_data handle. The vpe_dev holds the csc_data handle. The handle represents an instance of the CSC hardware, and the vpe driver uses it to access the CSC register offsets or helper functions to configure these registers. The CSC register offsets are now relative to the CSC block itself, so we need to use the macro GET_OFFSET_TOP to get the CSC register offset relative to the VPE IP in the vpe driver. Signed-off-by:
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Archit Taneja authored
Add the required SC register configurations which lets us perform linear scaling for the supported range of horizontal and vertical scaling ratios. The horizontal scaler performs polyphase scaling using it's 8 tap 32 phase filter, decimation is performed when downscaling passes beyond 2x or 4x. The vertical scaler performs polyphase scaling using it's 5 tap 32 phase filter, it switches to a simpler form of scaling using the running average filter when the downscale ratio is more than 4x. Many of the SC features like peaking, trimming and non-linear scaling aren't implemented for now. Only the minimal register fields required for basic scaling operation are configured. The function to configure SC registers takes the sc_data handle, the source and destination widths and heights, and the scaler address data block offsets for the current context so that they can be configured. Signed-off-by:
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Archit Taneja authored
Make the driver allocate dma buffers to store horizontal and scaler coeffs. Use the scaler library api to choose and copy scaler coefficients to a the above buffers based on the scaling ratio. Since the SC block comes after the de-interlacer, make sure that the source height is doubled if de-interlacer was used. These buffers now need to be used by VPDMA to load the coefficients into the SRAM within SC. In device_run, add configuration descriptors which have payloads pointing to the scaler coefficients in memory. Use the members in sc_data handle to prevent addition of these descriptors if there isn't a need to re-load coefficients into SC. This comes helps unnecessary re-loading of the coefficients when we switch back and forth between vpe contexts. Signed-off-by:
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Archit Taneja authored
The SC block in VPE/VIP contains a SRAM within it. This internal memory requires to be loaded with appropriate scaler coefficients from a contiguous block of memory through VPDMA. The horizontal and vertical scaler each require 2 sets of scaler coefficients for luma and chroma scaling. The horizontal polyphase scaler requires coefficients for a 32 phase and 8 tap filter. Similarly, the vertical scaler requires coefficients for a 5 tap filter. The choice of the scaler coefficients depends on the scaling ratio. Add coefficient tables for different scaling ratios in sc_coeffs.h. In the case of horizontal downscaling, we need to consider the change in ratio caused by decimation performed by the horizontal scaler. In order to load the scaler coefficients via VPDMA, a configuration descriptor is used in block mode. The payload for the descriptor is the scaler coefficients copied to memory. Coefficients for each phase have to be placed in memory in a particular order understood by the scaler hardware. The choice of the scaler coefficients, and the loading of the coefficients from our tables to a contiguous buffer is managed by the functions sc_set_hs_coefficients and sc_set_vs_coefficients. The sc_data handle is now added with some parameters to describe the state of the coefficients loaded in the SC block. 'loaded_coeff_h' and 'loaded_coeff_v' hold the address of the last dma buffer which was used by VPDMA to copy coefficients. This information can be used by a vpe mem-to-mem context to decide whether it should load coefficients or not. 'hs_index' and 'vs_index' provide some optimization by preventing loading of coefficients if the scaling ratio didn't change between 2 contexts. 'load_coeff_h' and 'load_coeff_v' tell the vpe/vip driver whether we need to load the coefficients through VPDMA or not. Signed-off-by:
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Archit Taneja authored
VPE and VIP IPs in DAR7x contain a scaler(SC) sub block. Create a library which will perform scaler block related configurations and hold SC register definitions. The functions provided by this library will be called by the vpe and vip drivers using a sc_data handle. The vpe_dev holds the sc_data handle. The handle represents an instance of the SC hardware, and the vpe driver uses it to access the scaler register offsets or helper functions to configure these registers. We move the SC register definitions to sc.h so that they aren't specific to VPE anymore. The register offsets are now relative to the sub-block, and not the VPE IP as a whole. In order for VPDMA to configure registers, it requires it's offset from the top level VPE module. A macro called GET_OFFSET_TOP is added to return the offset of the register relative to the VPE IP. Signed-off-by:
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Hans Verkuil authored
The (d)qbuf ioctls were traced in the low-level v4l2 ioctl function. The trace was outside the serialization lock, so that can affect the usefulness of the timing. In addition, the __user pointer was expected instead of a proper kernel pointer. By moving the tracepoints to video_usercopy we ensure that the trace calls use the correct kernel pointer, and that it happens right after the ioctl call to the driver, so certainly inside the serialization lock. In addition, we only trace if the call was successful. Signed-off-by:
Wade Farnsworth <wade_farnsworth@mentor.com> Signed-off-by:
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Antonio Ospite authored
Change "packet" to "packed" where the doc is talking about packed data formats. Signed-off-by:
Antonio Ospite <ospite@studenti.unina.it> Signed-off-by:
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Antonio Ospite authored
The xref to the v4l2-mbus-pixelcode-yuv8 table gets rendered as "Table 4.22, “YUV Formats”", so use the verb in the third person singular because it refers to "Table": s/list/lists/ Signed-off-by:
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Matthias Schwarzott authored
Do not shift the already 7bit i2c address. Print a message also for write+read transactions. For write+read, print the read buffer correctly instead of using the write buffer. Signed-off-by:
Matthias Schwarzott <zzam@gentoo.org> Signed-off-by:
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Matthias Schwarzott authored
The two drivers LGDT3305 and TDA18271C2DD were not autoselected, so the cx231xx_dvb module could not be loaded when MEDIA_SUBDRV_AUTOSELECT=y. Signed-off-by:
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Wei Yongjun authored
Add the missing unlock before return from function bcm2048_rds_fifo_receive() in the error handling case. Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by:
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Hans Verkuil authored
Add a proper driver strength enum and use the same names in the platform data as with adv7604. Signed-off-by:
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Hans Verkuil authored
This timing must be supported by all HDMI equipment, so that's a reasonable default. Signed-off-by:
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Hans Verkuil authored
The correct LLC DLL phase depends on the board layout, so this should be part of the platform_data. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Tested-by:
Martin Bugge <marbugge@cisco.com> Signed-off-by:
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Martin Bugge authored
Return 0 if the new timings are equal to the current timings as it caused extra cp-loss/lock interrupts. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
The free-run mode can be board-specific. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Signed-off-by:
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Martin Bugge authored
Must clear timings before setting after test to recover. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
Clear i2c_clients ptr when unregistered. Warn if configured i2c-addr is zero. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
The STDI block may measure wrong values, especially for lcvs and lcf. If the driver can not find any valid timing, the STDI block is restarted to measure the video timings again. The function will return an error, but the restart of STDI will generate a new STDI interrupt and the format detection process will restart. Copied from adv7604. Signed-off-by:
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Martin Bugge authored
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Mats Randgaard authored
Signed-off-by:
Mats Randgaard <matrandg@cisco.com> Signed-off-by:
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Mats Randgaard authored
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Mats Randgaard authored
May also be wrong if the receiver is connected to more than one connector. Signed-off-by:
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Martin Bugge authored
Wait 5ms after main reset. The data-sheet doesn't specify the wait after i2c-controlled reset, so using same value as after pin-controlled reset. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
Both the PAL and NTSC standards are interlaced where a frame consist of two fields. Total number of lines in a frame in both systems are an odd number so the two fields will have different length. In the 625 line standard ("PAL") the odd field of the frame is transmitted first, while in the 525 standard ("NTSC") the even field is transmitted first. This adds the possibility to change output config between the fields and standards. This setting will reduce the "format-jitter" on the signal sent by the pixelport moving the difference between the fields to vertical front/back-porch only. Signed-off-by: -
Martin Bugge authored
For edid with no Source Physical Address (spa), set spa-location to default and use correct values from edid. Signed-off-by:
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Hans Verkuil authored
Added support for YCrCb analog input. If input is ADV7842_MODE_RGB and RGB quantization range is set to V4L2_DV_RGB_RANGE_AUTO, then video with CEA timings will be received as RGB. For ADV7842_MODE_COMP, automatic CSC mode will be selected. See table 48 on page 281 in "ADV7842 Hardware Manual, Rev. 0, January 2011" for details. Make sure that when switching inputs the RGB quantization range is updated as well. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
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Martin Bugge authored
The method of disabling the irq-output pin caused many "empty" interrupts. Instead, actually disable/enable the interrupts by changing the interrupt masks. Also enable STORE_MASKED_IRQ in INT1 configuration, otherwise when HDMI events happen while the interrupt is masked those events will be ignored when the interrupt is unmasked. Signed-off-by:
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Martin Bugge authored
Bit 6 of register 0x8f was cleared incorrectly (must be 1), and bit 4 of register 0x91 was set incorrectly (must be 0). These bits are undocumented, so we shouldn't modify them to values different from what the datasheet specifies. Signed-off-by:
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Martin Bugge authored
This simplified the code quite a bit. Signed-off-by:
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Hans Verkuil authored
This timing must be supported by all HDMI equipment, so that's a reasonable default. Signed-off-by:
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Martin Bugge authored
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