1. 03 Oct, 2014 1 commit
    • Dmitry Lavnikevich's avatar
      ASoC: tlv320aic3x: fix PLL D configuration · 31d9f8fa
      Dmitry Lavnikevich authored
      Current caching implementation during regcache_sync() call bypasses
      all register writes of values that are already known as default
      (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5
      (AIC3X_PLL_PROGC_REG) write should be immediately followed by register
      6 write (AIC3X_PLL_PROGD_REG) even if it was not changed. Otherwise
      both registers will not be written.
      
      This brings to issue that appears particulary in case of 44.1kHz
      playback with 19.2MHz master clock. In this case AIC3X_PLL_PROGC_REG
      is 0x6e while AIC3X_PLL_PROGD_REG is 0x0 (same as register
      default). Thus AIC3X_PLL_PROGC_REG also remains not written and we get
      wrong playback speed.
      
      In this patch snd_soc_read() is used to get cached pll values and
      snd_soc_write() (unlike regcache_sync() this function doesn't bypasses
      hardware default values) to write them to registers.
      Signed-off-by: default avatarDmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
      Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      Cc: stable@vger.kernel.org
      31d9f8fa
  2. 16 Aug, 2014 39 commits