- 24 Jan, 2014 22 commits
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Ganesan Ramalingam authored
XLP9XX has a USB 3.0 controller on-chip with 2 xHCI ports. The USB block is similar to the one on XLP2XX, so update usb-init-xlp2.c to handle XLP9XX as well. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6285/
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Jayachandran C authored
Add PCI support for Netlogic XLP9XX. The PCI registers and SoC bus numbers have changed in XLP9XX. Also skip a few (bus,dev,fn) combinations which have issues when read. Signed-off-by:
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Jayachandran C authored
XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX. Update code that calculates node id from cpu id to handle this. Signed-off-by:
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Jayachandran C authored
Update bridge code. Add code to the XLP9XX registers for DRAM size, limit and node when running on XLPXX Signed-off-by:
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Jayachandran C authored
Update IO offset of the early console UART. Signed-off-by:
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Jayachandran C authored
Add the SYS block registers for XLP9XX, most of them have changed. The wakeup sequence has been updated to set the coherent mode from the main thread rather than the woken up thread. Signed-off-by:
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Jayachandran C authored
Functions for the XLP9XX interrupt table entry format and other PIC register changes. Signed-off-by:
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Jayachandran C authored
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the new addresses of different SoC blocks like PIC, SYS, UART etc. that are needed by the base code. On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus corresponding to the node. Update iomap code to reflect this. Signed-off-by:
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Jayachandran C authored
Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX. Signed-off-by:
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Jayachandran C authored
Use the FUSE register to get the list of active cores in the CPU instead of using the CPU reset register, this is the recommended method. Also add code to mask the coremask with the default number of cores for each processor series. Signed-off-by:
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Jayachandran C authored
Add macro nlm_node_present() that can be used to check if a node is present in a multi-chip configuration. This can be used even when NUMA is not enabled. Signed-off-by:
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Yonghong Song authored
On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by:
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Jayachandran C authored
No change in logic, the changes are: * cleanup some whitespace and comments * remove confusing argument of SYS_CPU_COHERENT_BASE macro * make the numerical labels in macros consistent Signed-off-by:
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Jayachandran C authored
Add mach-netlogic/topology.h which contains XLP cpu number to core and node mapping. Signed-off-by:
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Jayachandran C authored
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by:
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Deng-Cheng Zhu authored
Boot log says: pci 0000:00:0a.3: no compatible bridge window for [io 0x1000-0x103f] pci 0000:00:0a.3: no compatible bridge window for [io 0x1100-0x110f] The io resource starting point on Malta was modified by c5de50da (MIPS: Malta: Change start address to avoid conflicts.) to avoid conflicts with ACPI and SMB devices. In fact, that was not needed (and now causing southbridge ACPI missing) since 166c6370 (PCI: add pci_create_root_bus() that accepts resource list) and 7c090e5b (mips/PCI: convert to pci_scan_root_bus() for correct root bus resources) had already done the correct fix. This patch actually reverts the change made by c5de50da. And with this fix, log says: pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI pci 0000:00:0a.3: quirk: [io 0x1100-0x110f] claimed by PIIX4 SMB These things may not be used but as part of platform resources are better off to be included. Cc: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by:
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Aaro Koskinen authored
Currently the supported ISA is only printed on the latest architectures. Print it also on legacy platforms. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
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Apelete Seketeli authored
The platform data already available in tree for JZ4740 USB Device Controller was previously used by an out-of-tree USB gadget driver which was not relying on the musb driver and was written by Ingenic and the Qi-Hardware community. Update platform data for JZ4740 USB device controller to be used with musb driver. Signed-off-by:
Apelete Seketeli <apelete@seketeli.net> Acked-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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Eunbong Song authored
This patch removes CONFIG_MTD_PARTITIONS in config files for MIPS. Because CONFIG_MTD_PARTITIONS was removed by commit 6a8a98b2. Signed-off-by:
Eunbong Song <eunb.song@samsung.com>
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Paul Burton authored
There is already an init_dsp function which checks cpu_has_dsp & calls __init_dsp if it does. Make use of it instead of duplicating the same code. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Signed-off-by:
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Paul Burton authored
This patch cleans up the declaration of the resume function by replacing void pointers with their correct types. The irrelevant & incorrect comment preceeding the resume function is replaced by one documenting its function. Signed-off-by:
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Apelete Seketeli authored
Add defconfig for the Ben NanoNote handheld computer which is built around QI_LB60 board and Ingenic JZ4740 MIPS SoC. Signed-off-by:
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- 23 Jan, 2014 18 commits
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Rafał Miłecki authored
Input GPIO changes can generate interrupts, but we need kind of ACK for them by changing IRQ polarity. This is required to stop hardware from keep generating interrupts and generate another one on the next GPIO state change. This code allows using GPIOs with standard interrupts and add for example GPIO buttons support. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by:
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Qais Yousef authored
The file uses u16 type but doesn't include its definition explicitly I was getting this error when including this header in my driver: arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’ Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Acked-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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Qais Yousef authored
we want the device tree to be unflattened into non init memory so it can be accessed later by, for example, a probing function of a driver module. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Qais Yousef authored
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Qais Yousef authored
The defaults are not always applicable and it makes it hard for the bootloader to override them. By removing it we give the bootloader full control over what command line parameters to pass. Without this change we will need to modify the built-in dtb to add bootloader cmd line parameters or do some work to append them after we unflatten the device tree. Sead3 is a development board, that's why we want to be able to change boot parameters on the fly from the bootloader. Signed-off-by:
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Qais Yousef authored
if the user sets memsize parameter in commandline or bootloader environment, we use it to modify the built-in dtb memory size Signed-off-by:
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Florian Fainelli authored
Update the early_printk code to include linux/serial_bcm63xx.h which provides the definitions for the UART block registers. While at it, remove the inclusion of serial_bcm63xx.h which was just there to allow smooth transition. Signed-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
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Florian Fainelli authored
Now that the UART block defines have been moved to a separate file, include that one and do not longer rely on the MIPS-specific bcm63xx_regs.h header file. Signed-off-by:
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Florian Fainelli authored
Move the BCM63XX UART driver definitions to include/linux/serial_bcm63xx.h such that we do not rely on the MIPS BCM63XX code to provide these for us. Signed-off-by:
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Florian Fainelli authored
bcm_{readl,writel} macros expand to __raw_{readl,writel}, use these directly such that we do not rely on the platform to provide these for us. As a result, we no longer use bcm63xx_io.h, so remove that inclusion too. Signed-off-by: -
Florian Fainelli authored
bcm63xx_irqs.h is included but we are not using anything from it, drop that include. Signed-off-by:
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Steven J. Hill authored
Remove usage of -mno-jals compiler flag when building a pure microMIPS kernel. The -mno-jals flag only ever existed within Mentor toolchains. Dropping this flag allows all FSF toolchains to work. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:
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David Daney authored
This will be needed by the next patch to use said nodes for probing via the device tree. Signed-off-by:
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Paul Burton authored
This patch switches Malta from using the MIPS implementation of early printk with Malta's prom_putchar to using the generic 8250_early implementation. This offers a couple of advantages: - We duplicate less generic code. - The UART can be initialised rather than being reliant upon inheriting a valid setup from the bootloader. The Malta console_config function is extended to initialise the early console if no earlycon= kernel parameter is provided, inheriting the modetty0 bootloader environment if present and falling back to a default 38400n8r setup if not. This matches the behaviour used for the regular console= parameter. Signed-off-by: -
Paul Burton authored
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by:
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Paul Burton authored
The RTC is used on Malta to estimate the clock frequency of the CPU & optionally the GIC. However the kernel previously did not initialise the RTC, instead relying upon the bootloader having done so. In order to minimise dependencies which the kernel has upon the bootloader this patch causes the kernel to initialise the RTC itself prior to making use of it. Signed-off-by:
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Paul Burton authored
This variable seems to have been copied from Malta when SEAD3 support was introduced, but is likewise unused. Remove it. Signed-off-by:
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Paul Burton authored
This variable was introduced by commit 96348c8f (of Ralf's historic Linux/MIPS repository) "Remaining fixes for MIPS's eval boards." but I don't see any use of it either then or now. Remove it. Signed-off-by:
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