- 22 Nov, 2014 14 commits
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Arnaud Ebalard authored
Synology DS414 is a 4-bay NAS powered by a Marvell Armada XP (mv78230 dual-core @1.33Ghz). It is very similar on many aspects to previous 4-bay synology models based on Marvell kirkwood SoC. Here is a short summary of the device: - 1GB RAM - Boot on SPI flash (64Mbit Micron N25Q064) - 2 GbE interfaces (Armada MAC connected to two Marvell 88E1512 PHY via RGMII) - 1 front USB 2.0 ports (directly handled by the Armada 370) - 2 rear USB 3.0 ports (handled by an EtronTech EJ168A XHCI controller on the PCIe bus) - 4 internal SATA ports handled by a Marvell 88SX7042 SATA-II controller on the PCIe bus) - Seiko S-35390A I2C RTC chip - UART0 providing serial console - UART1 used for poweroff (connected to a Microchip PIC16F883) Additional note: the front LEDs the and the two fans are not directly connected to the SoC and under its control. The former are presumably driven by the SATA controller, the latter by the PIC. [ jac: fixed up s/ge[01]_rgmii_pins/pmx_ge[01]_rgmii/ to match armada-xp.dtsi ] Acked-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/5b678d6d1f2f42f4bf0d087878b9d8024d463ea7.1416613429.git.arno@natisbad.orgSigned-off-by:
Jason Cooper <jason@lakedaemon.net>
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Arnaud Ebalard authored
Synology DS213j is a 2-bay NAS powered by a Marvell Armada 370 (88F6710 @1.2Ghz). It is very similar on many aspects to previous 2-bay synology models based on Marvell kirkwood SoC. Here is a short summary of the device: - 512MB RAM - boot on SPI flash (64Mbit Micron N25Q064) - 1 GbE interface (Armada MAC connected to a Marvell 88E1512 PHY via SGMII) - 2 rear USB 2.0 ports (directly handled by the Armada 370) - 2 internal SATA ports handled by the Armada 370: 2 GPIO for presence, 2 for powering them - two front amber LED (disk1, disk2) controlled by the SoC - Seiko S-35390A I2C RTC chip - UART0 providing serial console - UART1 used for poweroff (connected to a TI MSP430F2111) - Fan handled via 4 GPIO (3 for speed, 1 for alarm) Acked-by:
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Arnaud Ebalard authored
This patch defines common Armada XP pinctrl settings in armada-xp.dtsi for the supported SPI interface (MPP36-39) and use it as default for Armada XP spi interface. That being done, it removes the now redundant definitions in armada-xp-axpwifiap.dts. Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their spi interfaces if the default above does not match their config (i.e. if they do not use CS0). Acked-by:
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Arnaud Ebalard authored
This patch defines common Armada XP pinctrl settings for uart2 and uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP): uart2: MPP42-43 as default uart3: MPP44-45 as default Suggested-by:
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Arnaud Ebalard authored
This patch defines common Armada 370 pinctrl settings for uart0 and uart1 interfaces: uart0: MPP0-1 as default uart1: MPP41-42 as default Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their uart interfaces if the default above does not match their config. Suggested-by:
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Arnaud Ebalard authored
This patch defines common Armada 370 pinctrl settings for spi0 and spi1 interfaces: spi0: MPP33-36 as default, MPP32,63-65 as available alternate config spi1: MPP49-52 as default Currently, the Armada 370 DB .dts file has no explicit pinctrl info for the spi0 interface used to access the flash on the board. The patch fixes that by also adding explicit pinctrl info (MPP32,63-65) for this SPI interface. Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their spi interfaces if the default above does not match their config. Suggested-by:
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Arnaud Ebalard authored
What was done by Sebastian in 264a05e1 ("ARM: mvebu: armada-xp: Add node alias to pinctrl and add base address") and 01c43422 ("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for Armada 370, i.e. - Rename Armada 370 pinctrl node to pin-ctrl with its address encoded - Add a node alias to access the pinctrl node easily. - use the newly available alias in existing Armada 370 .dts files We can even go a bit further by putting the pinctrl node definition in armada-370-xp.dtsi, with only its reg property defined. This allows us to then also use the newly defined node alias in armada-xp.dtsi, armada-370.dtsi. Suggested-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Suggested-by:
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Arnaud Ebalard authored
Now that labels for uartX are available in Marvell Armada .dtsi files, this patch replaces the "/soc/internal-regs/serial@12000" found in armada-xp-lenovo-ix4-300d.dts file for stdout-path property by the more concise &uart0. Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by:
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Arnaud Ebalard authored
This patch adds uartX labels for Armada SoC serial nodes. This is a preliminary work to be able to easily reference the serial lines in Device Tree files. One expected use is when providing stdout-path property for barebox. Reviewed-by:
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Arnaud Ebalard authored
As reported by Andrew, the vendor prefix for Seiko Instruments, Inc. S-35390A I2C RTC chip in kirkwood-synology.dtsi has a typo (ssi instead of sii). This patches fixes it. Note: i2c devices ignore the optional vendor prefix, which explains why it worked with the typo and also why there is no backward compatibility issues with the fix. Reported-by:
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Uwe Kleine-König authored
Commit a095b1c7 ("ARM: mvebu: sort DT nodes by address") missed placing the system-controller in the correct order. Fixes: a095b1c7 ("ARM: mvebu: sort DT nodes by address") Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
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Marcin Wojtas authored
In order to update MAC address entries in the ethernet nodes in Device Tree both mainline U-Boot and Barebox bootloaders accept the same format of aliases, which is 'ethernetX', where X stands for an interface number. Other platforms in the mainline Linux, that comprise ethernet references in '/aliases' node (like various flavours of imx or sunXi), follow the naming scheme described above. This commit ajusts ethernet aliases of Marvell Armada 38x SoC to be properly recognized by bootloaders' MAC address fixup routines. Signed-off-by:
Marcin Wojtas <mw@semihalf.com> Reviewed-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
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Marcin Wojtas authored
For proper operation of Armada 38x SDHCI controller proper 'clocks' property is sufficient. Therefore it is not useful to keep an additional 'clock-frequency' property in SDHCI controller node of board-level Device Tree file for Armada 385 DB. This commit gets rid of useless 'clock-frequency' property. Signed-off-by:
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Marcin Wojtas authored
The Marvell Armada 38x SoC's SDHCI interface is capable of using 1.8v voltage, needed for driving "UHS-I" SD cards at their full speed. It is not, however, possible on the DB board. Due to physical connectivity connector supply is tied to 3v and any attempt of changing voltage in order to operate in the fastest UHS modes fails. This patch enables equivalent SDHCI quirk in order to adjust controller operation to system capabilities. Signed-off-by:
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- 07 Nov, 2014 3 commits
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Andrew Lunn authored
The 370 rd has a 7 port, mv88E6182 switch, connected to eth1. Add a fixed-link subnode to the ethernet device tree node, to force gigabit/full duplex. Add a dsa node, with describing the four used ports. This requires adding an alias to the mdio node, so it can be referenced as a phandle. Signed-off-by:
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Thomas Petazzoni authored
This commit modifies the Armada 370 and Armada 370 DB Device Tree descriptions to use the simple-card DT binding to describe the audio complex of the Armada 370 DB instead of a custom audio machine driver. To do so, it: - Adds the sound-dai-cells properties to the CS42L51 node, the audio controller node and the SPDIF in/out nodes. - Completely changes the description of the sound complex to use the "simple-audio-card" DT binding instead of the "marvell,a370db-audio" DT binding. - Fixes the indentation to properly use tabs instead of spaces. Signed-off-by:
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Thomas Petazzoni authored
Back when audio was enabled, the muxing of some MPP pins was causing problems. However, since commit fea038ed ("ARM: mvebu: Add proper pin muxing on the Armada 370 DB board"), those problematic MPP pins have been assigned a proper muxing for the Ethernet interfaces. This proper muxing is now conflicting with the hog pins muxing that had been added as part of 249f3822 ("ARM: mvebu: add audio support to Armada 370 DB"). Therefore, this commit simply removes the hog pins muxing, which solves a warning a boot time due to the conflicting muxing requirements. Fixes: fea038ed ("ARM: mvebu: Add proper pin muxing on the Armada 370 DB board") Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
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- 02 Nov, 2014 8 commits
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Sebastian Hesselbarth authored
There is only one 74hc595 connected to GPIO but two were given in the registers-number property. Fix it up. Signed-off-by:
Benoit Masson <yahoo@perenite.com> Signed-off-by:
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Sebastian Hesselbarth authored
There is an I2C eeprom connected on Lenovo ix4-300d, add the corresponding node. Signed-off-by:
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Sebastian Hesselbarth authored
Lenovo ix4-300d has two ethernet PHYs connected via RGMII. Add the corresponding pinctrl settings. Signed-off-by:
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Sebastian Hesselbarth authored
There is a GMII setting for GE0, add it to the common pinctrl node. Signed-off-by:
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Sebastian Hesselbarth authored
Pinctrl settings for GE0 and GE1 are not only usable on RD-AXPWiFiAP. Moreover, naming the RGMII settings pmx-ge{0,1} is not precise enough as there is also a GMII setting for GE0. Move the pinctrl sub-nodes to the common pinctrl node and rename them to pmx-ge{0,1}-rgmii. Signed-off-by: -
Sebastian Hesselbarth authored
Armada XP pinctrl node gained an alias, make use of it. Signed-off-by:
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Sebastian Hesselbarth authored
In other MVEBU SoCs, the pin controller node is called pin-ctrl with its base address added. Also, we have a node alias to access the pinctrl node easily. Fix this for Armada XP pinctrl nodes to be consistent with other SoCs. Signed-off-by:
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Sebastian Hesselbarth authored
All current Armada XP SoCs have their pin controller at 0x18000/0x38. Move the common properties of pinctrl nodes to armada-xp.dtsi to allow to share pinctrl settings later. Signed-off-by:
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- 01 Nov, 2014 7 commits
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Andrew Lunn authored
The DIR665 has an 8 port Ethernet Switch, a Marvell mv88e6171. Add a DSA node in DT, to instantiate DSA support for the 4 back panel ports, the Internet port, and the port to the CPU which is connected to eth0. Signed-off-by:
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Claudio Leite authored
Add a device tree description of the DLINK DIR665 wireless access point. The support for the 88E6171 switch will be added in a later patch. Signed-off-by:
Claudio Leite <leitec@staticky.com> Signed-off-by:
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Arnaud Ebalard authored
NETGEAR ReadyNAS 2120 supports its four main SATA disks via 2 Marvell 88SE9170 SATA controllers connected on the PCIe bus of the the SoC. The two eSATA ports available at the rear of the device are handled by the native SATA controller of the Armada XP SoC powering the NAS. This patch enables the SoC SATA controller in the .dts file to make those two rear ports available. Signed-off-by:
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Ezequiel Garcia authored
Now that the timer and watchdog drivers support the Armada 375 usage of the reference clock, we can enable it in the devicetree. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by:
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Arnaud Ebalard authored
On NETGEAR ReadyNAS 102, the two disks are connected to the external Marvell 88SE9170 SATA Controller connected to the PCIe bus. The rear eSATA port is connected to the native Armada 370 SATA controller. This patch updates the comments in .dts file wrt SATA interfaces and reduces the number of ports for native Armada 370 interface from 2 to 1. Signed-off-by:
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Arnaud Ebalard authored
When writing initial .dts file for NETGEAR ReadyNAS 102, I put the wrong color for backup and SATA leds (green instead of blue for all three). Reported-by:
Johan Kristell <johan.kristell@gmail.com> Signed-off-by:
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Gregory CLEMENT authored
The L2 cache controller on the Armada 370 and Armada XP SoCs is a unified cache. Moreover, the Aurora cache controller is compatible with the L2x0 cache controller: the "cache-unified" property is required by its binding. This patch fixes the Aurora L2 cache node for the Armada 370 and Armada XP SoCs by adding this property. Reported-by:
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- 20 Oct, 2014 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds authored
Pull ARM SoC fixes from Olof Johansson: "A batch of fixes that have come in during the merge window. Some of them are defconfig updates for things that have now landed, some errata additions and a few general scattered fixes. There's also a qcom DT update that adds support for SATA on AP148, and basic support for Sony Xperia Z1 and CM-QS600 platforms that seemed isolated enough that we could merge it even if it's late" * tag 'arm-soc-fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: MAINTAINERS: corrected bcm2835 search ARM: dts: Explicitly set dr_mode on exynos5420-arndale-octa ARM: dts: Explicitly set dr_mode on exynos Peach boards ARM: dts: qcom: add CM-QS600 board ARM: dts: qcom: Add initial DTS file for Sony Xperia Z1 phone ARM: dts: qcom: Add SATA support on IPQ8064/AP148 MAINTAINERS: Update Santosh Shilimkar's email id ARM: sunxi_defconfig: enable CONFIG_REGULATOR ARM: dts: Disable smc91x on n900 until bootloader dependency is removed ARM: omap2plus_defconfig: Enable ARM erratum 430973 for omap3 ARM: exynos_defconfig: enable USB gadget support ARM: exynos_defconfig: Enable Maxim 77693 and I2C GPIO drivers ARM: mm: Fix ifdef around cpu_*_do_[suspend, resume] ops ARM: EXYNOS: Fix build with PM_SLEEP=n and ARM_EXYNOS_CPUIDLE=n ARM: SAMSUNG: Restore Samsung PM Debug functionality ARM: dts: Fix pull setting in sd4_width8 pin group for exynos4x12 ARM: exynos_defconfig: Enable SBS battery support ARM: exynos_defconfig: Enable Control Groups support ARM: exynos_defconfig: Enable Atmel maXTouch support ARM: exynos_defconfig: Enable MAX77802
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- 19 Oct, 2014 6 commits
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git://git.infradead.org/users/eparis/auditLinus Torvalds authored
Pull audit updates from Eric Paris: "So this change across a whole bunch of arches really solves one basic problem. We want to audit when seccomp is killing a process. seccomp hooks in before the audit syscall entry code. audit_syscall_entry took as an argument the arch of the given syscall. Since the arch is part of what makes a syscall number meaningful it's an important part of the record, but it isn't available when seccomp shoots the syscall... For most arch's we have a better way to get the arch (syscall_get_arch) So the solution was two fold: Implement syscall_get_arch() everywhere there is audit which didn't have it. Use syscall_get_arch() in the seccomp audit code. Having syscall_get_arch() everywhere meant it was a useless flag on the stack and we could get rid of it for the typical syscall entry. The other changes inside the audit system aren't grand, fixed some records that had invalid spaces. Better locking around the task comm field. Removing some dead functions and structs. Make some things static. Really minor stuff" * git://git.infradead.org/users/eparis/audit: (31 commits) audit: rename audit_log_remove_rule to disambiguate for trees audit: cull redundancy in audit_rule_change audit: WARN if audit_rule_change called illegally audit: put rule existence check in canonical order next: openrisc: Fix build audit: get comm using lock to avoid race in string printing audit: remove open_arg() function that is never used audit: correct AUDIT_GET_FEATURE return message type audit: set nlmsg_len for multicast messages. audit: use union for audit_field values since they are mutually exclusive audit: invalid op= values for rules audit: use atomic_t to simplify audit_serial() kernel/audit.c: use ARRAY_SIZE instead of sizeof/sizeof[0] audit: reduce scope of audit_log_fcaps audit: reduce scope of audit_net_id audit: arm64: Remove the audit arch argument to audit_syscall_entry arm64: audit: Add audit hook in syscall_trace_enter/exit() audit: x86: drop arch from __audit_syscall_entry() interface sparc: implement is_32bit_task sparc: properly conditionalize use of TIF_32BIT ...
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Olof Johansson authored
Merge tag 'qcom-dt-for-3.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into fixes Merge "qcom DT changes for v3.18-3" from Kumar Gala: Qualcomm ARM Based Device Tree Updates for v3.18-3 * Added Board support for CM-QS600 and Sony Xperia Z1 phone * Added SATA support on IPQ8064/AP148 * tag 'qcom-dt-for-3.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: dts: qcom: add CM-QS600 board ARM: dts: qcom: Add initial DTS file for Sony Xperia Z1 phone ARM: dts: qcom: Add SATA support on IPQ8064/AP148
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Olof Johansson authored
Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes Pull more fixes from Kukjin Kim: 2nd Samsung fixes for v3.18 - Explicitly set dr_mode on exynos5800-peach-pi, exynos5420-peach-pit and exynos5420-arndale-octa boards, because the USB dwc3 controller will not work properly without dr_mode as host on above boards if the USB host and gadget are enabled in kernel configuration both. * tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Explicitly set dr_mode on exynos5420-arndale-octa ARM: dts: Explicitly set dr_mode on exynos Peach boards Signed-off-by:
Olof Johansson <olof@lixom.net>
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Scott Branden authored
Corrected bcm2835 maintainer info by using N: to specify any files with bcm2835 in are directed to the proper maintainer. Also corrected minor mispelling of ARCHITECTURE in 2 comment locations. Signed-off-by:
Scott Branden <sbranden@broadcom.com> Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
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git://github.com/jonmason/ntbLinus Torvalds authored
Pull ntb (non-transparent bridge) updates from Jon Mason: "Add support for Haswell NTB split BARs, a debugfs entry for basic debugging info, and some code clean-ups" * tag 'ntb-3.18' of git://github.com/jonmason/ntb: ntb: Adding split BAR support for Haswell platforms ntb: use errata flag set via DID to implement workaround ntb: conslidate reading of PPD to move platform detection earlier ntb: move platform detection to separate function NTB: debugfs device entry
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git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linuxLinus Torvalds authored
Pull i2c updates from Wolfram Sang: "Highlights from the I2C subsystem for 3.18: - new drivers for Axxia AM55xx, and Hisilicon hix5hd2 SoC. - designware driver gained AMD support, exynos gained exynos7 support The rest is usual driver stuff. Hopefully no lowlights this time" * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: i801: Add Device IDs for Intel Sunrise Point PCH i2c: hix5hd2: add i2c controller driver i2c-imx: Disable the clock on probe failure i2c: designware: Add support for AMD I2C controller i2c: designware: Rework probe() to get clock a bit later i2c: designware: Default to fast mode in case of ACPI i2c: axxia: Add I2C driver for AXM55xx i2c: exynos: add support for HSI2C module on Exynos7 i2c: mxs: detect No Slave Ack on SELECT in PIO mode i2c: cros_ec: Remove EC_I2C_FLAG_10BIT i2c: cros-ec-tunnel: Add of match table i2c: rcar: remove sign-compare flaw i2c: ismt: Use minimum descriptor size i2c: imx: Add arbitration lost check i2c: rk3x: Remove unlikely() annotations i2c: rcar: check for no IRQ in rcar_i2c_irq() i2c: rcar: make rcar_i2c_prepare_msg() *void* i2c: rcar: simplify check for last message i2c: designware: add support of platform data to set I2C mode i2c: designware: add support of I2C standard mode
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