- 22 Mar, 2018 3 commits
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Deepak Rawat authored
The function drm_crtc_arm_vblank_event should be used for the driver which have vblank interrupt support. In case of vmwgfx we do not have vblank interrupt. Signed-off-by:
Deepak Rawat <drawat@vmware.com> Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com>
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Deepak Rawat authored
When display surface is different than the framebuffer surface, atomic path do not copy the surface data. This commit moved the code to copy surface from legacy to atomic path. Signed-off-by:
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Deepak Rawat authored
In case of page flip there is no need to iterate over all display unit in the function "vmw_kms_helper_dirty". If crtc is available then dirty commands is performed on that crtc only. Signed-off-by:
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- 21 Mar, 2018 5 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linuxDave Airlie authored
omapdrm patches for v4.17 * Fix sparse warnings from omapdrm * HPD support for DVI connector * Big cleanup to remove static variables * tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (69 commits) drm/omap: fix compile error when DPI is disabled drm/omap: fix compile error when debugfs is disabled drm: omapdrm: displays: panel-dsi-cm: Fix field access before set drm/omap: cleanup color space conversion drm/omap: Allow HDMI audio setup even if we do not have video configured drm/omap: fix maximum sizes drm/omap: add writeback funcs to dispc_ops drm/omap: fix scaling limits for WB drm/omap: fix WB height with interlace drm/omap: fix WBDELAYCOUNT with interlace drm/omap: fix WBDELAYCOUNT for HDMI drm/omap: set WB channel-in in wb_setup() drm/omap: Add pclk setting case when channel is DSS_WB drm/omap: dispc: disp_wb_setup to check return code drm/omap: remove leftover enums dt-bindings: display: add HPD gpio to DVI connector drm/omap: add HPD support to connector-dvi drm/omap: Init fbdev emulation only when we have displays drm/omap: cleanup fbdev init/free drm/omap: fix omap_fbdev_free() when omap_fbdev_create() wasn't called ...
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git://people.freedesktop.org/~robclark/linuxDave Airlie authored
Updates for 4.17. Sorry, running a bit late on this, didn't have a chance to send pull-req before heading to linaro. But it has all been in linux-next for a while. Main updates: + DSI updates from 10nm / SDM845 + fix for race condition with a3xx/a4xx fence completion irq + some refactoring/prep work for eventual a6xx support (ie. when we have a userspace) + a5xx debugfs enhancements + some mdp5 fixes/cleanups to prepare for eventually merging writeback support (ie. when we have a userspace) * tag 'drm-msm-next-2018-03-20' of git://people.freedesktop.org/~robclark/linux: (36 commits) drm/msm: fix building without debugfs drm/msm/mdp5: don't pre-reserve LM's if no dual-dsi drm/msm/mdp5: add missing LM flush bits drm/msm/mdp5: print a bit more of the atomic state drm/msm/mdp5: rework CTL START signal handling drm/msm: Trigger fence completion from GPU drm/msm/dsi: fix direct caller of msm_gem_free_object() drm/msm: strip out msm_fence_cb drm/msm: rename mdp->disp drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_init drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereference drm/msm/dsi: Get byte_intf_clk only for versions that need it drm/msm/adreno: Use generic function to load firmware to a buffer object drm/msm/adreno: Define a list of firmware files to load per target drm/msm/adreno: Rename gpmufw to powerfw drm/msm: Pass the correct aperture end to drm_mm_init drm/msm/gpu: Set number of clocks to 0 if the list allocation fails drm/msm: Replace gem_object deprecated functions drm/msm/hdmi: fix semicolon.cocci warnings drm/msm/mdp5: Fix trailing semicolon ...
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v4.17-rc1 This fixes mmap() for fbdev devices by providing a custom implementation based on the KMS variant. This is a fairly exotic case these days, hence why it is not flagged for stable. There is also support for dedicating one of the overlay planes to serve as a hardware cursor on older Tegra that did support hardware cursors but not RGBA formats for it. Planes will now also export the IN_FORMATS property by supporting the various block-linear tiling modifiers for RGBA pixel formats. Other than that, there's a bit of cleanup of DMA API abuse, use of the private object infrastructure for global state (rather than subclassing atomic state objects) and an implementation of ->{begin,end}_cpu_access callbacks for PRIME exported buffers, which allow users to perform cache maintenance on these buffers. * tag 'drm/tegra/for-4.17-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: prime: Implement ->{begin,end}_cpu_access() drm/tegra: gem: Map pages via the DMA API drm/tegra: hub: Use private object for global state drm/tegra: fb: Properly support linear modifier drm/tegra: plane: Support format modifiers drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra's drm/tegra: plane: Make tegra_plane_get_overlap_index() static drm/tegra: fb: Implement ->fb_mmap() callback drm/tegra: gem: Make __tegra_gem_mmap() available more widely drm/tegra: gem: Reshuffle declarations -
git://linux-arm.org/linux-ldDave Airlie authored
I have accumulated some patches as we went through some internal testing for mali-dp and I was waiting for the YUV2RGB patches to land in your tree. * 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld: drm: mali-dp: Add YUV->RGB conversion support for video layers drm: mali-dp: Turn off CRTC vblank when removing module. drm: arm: malidp: Use drm_atomic_helper_shutdown() to disable planes on removal drm: arm: malidp: Don't destroy planes manually in error handlers drm/mali-dp: Fix malidp_atomic_commit_hw_done() for event sending. drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha drm: mali-dp: Fix bug on scaling with rotation drm/mali-dp: Don't enable scaling engine for planes that only rotate. drm: mali-dp: Uninitialized variable in malidp_se_check_scaling() drm/mali-dp: Align pitch size to be multiple of bus burst read size. drm/mali-dp: Rotated planes need a larger pitch size.
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
- Continued cleanup and restructuring of powerplay - Fetch VRAM type from vbios rather than hardcoding for SOC15 asics - Allow ttm to drop its backing store when drivers don't need it - DC bandwidth calc updates - Enable DC backlight control pre-DCE11 asics - Enable DC on all supported asics - DC Fixes for planes due to the way our hw is ordered vs what drm expects - DC CTM/regamma fixes - Misc cleanup and bug fixes * 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits) amdgpu/dm: Default PRE_VEGA ASIC support to 'y' drm/amd/pp: Remove the cgs wrapper for notify smu version on APU drm/amd/display: fix dereferencing possible ERR_PTR() drm/amd/display: Refine disable VGA drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel drm/radeon: Don't turn off DP sink when disconnected drm/amd/pp: Rename file name cz_* to smu8_* drm/amd/pp: Replace function/struct name cz_* with smu8_* drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c drm/amd/pp: Remove dead header file pp_asicblocks.h drm/amd/pp: Delete dead code on cz_clockpowergating.c drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c drm/amdgpu: Remove wrapper layer of smu ip functions drm/amdgpu: Don't compared ip_block_type with ip_block_index drm/amdgpu: Plus NULL function pointer check drm/amd/pp: Move helper functions to smu_help.c drm/amd/pp: Replace rv_* with smu10_* drm/amd/pp: Fix function parameter not correct drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table ...
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- 19 Mar, 2018 11 commits
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Arnd Bergmann authored
The adreno driver stopped building when CONFIG_DEBUGFS is disabled: drivers/gpu/drm/msm/adreno/adreno_device.c: In function 'adreno_load_gpu': drivers/gpu/drm/msm/adreno/adreno_device.c:153:16: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' if (gpu->funcs->debugfs_init) { ^~ drivers/gpu/drm/msm/adreno/adreno_device.c:154:13: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' gpu->funcs->debugfs_init(gpu, dev->primary); ^~ This adds an #ifdef around the code that references the hidden pointer. Fixes: 331dc0bc ("drm/msm: add a5xx specific debugfs") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Rob Clark authored
If there is only a single DSI interface, don't reserve the first two layer-mixers for the dual-DSI use-case. This was causing problems for WB, not being able to assign a LM, on 8x16, which has only two LM's and a single DSI. Signed-off-by: -
Rob Clark authored
For some reason, layer-mixer 3 and 4 were missing. LM3 is used for writeback on 8x16. Signed-off-by: -
Rob Clark authored
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Rob Clark authored
For DSI cmd-mode and writeback, we need to write the CTL's START register to kick things off, but we only want to do that once both the encoder and the crtc have a chance to write their corresponding flush bits. The difficulty is that when there is a full modeset (ie. encoder state has changed) we want to defer the start until encoder->enable(). But if only plane's have changed, we want to do this from crtc->commit(). The start_mask was a previous attempt to handle this, but it didn't really do the right thing since atomic conversion. Instead track in the crtc state that the start should be deferred, set to try from encoder's (or in future writeback's) atomic_check(). This way the state is part of the atomic state, and rollback can work properly if an atomic test fails. Signed-off-by: -
Bjorn Andersson authored
Interrupt commands causes the CP to trigger an interrupt as the command is processed, regardless of the GPU being done processing previous commands. This is seen by the interrupt being delivered before the fence is written on 8974 and is likely the cause of the additional CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to wait for the GPU to go idle before triggering the interrupt. Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS which will cause a special CACHE_FLUSH_TS interrupt to be triggered from the GPU as the write event is processed. Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the workaround for A306. Suggested-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Rob Clark authored
This should be using drm_gem_object_put(). Also since this is done only in driver unload path, we don't need to synchronize setting tx_gem_obj to NULL, so juse use the _unlocked() variant. Signed-off-by: -
Rob Clark authored
Remnants of pre-dma_fence fencing which got left behind by mistake. Signed-off-by: -
Rob Clark authored
Since new display controller is called "dpu" instead of "mdp". Lets make the name of the toplevel directory for the display controllers a bit more generic. Signed-off-by:
Sean Paul <seanpaul@chromium.org>
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Gustavo A. R. Silva authored
_dev_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _dev_ has been null checked. Fixes: d4e7f38d70ef ("drm/msm/dsi: check msm_dsi and dsi pointers before use") Signed-off-by:Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by:
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Gustavo A. R. Silva authored
_minor_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _minor_ has been null checked. Fixes: 024ad8df763f ("drm/msm: add a5xx specific debugfs") Signed-off-by:
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- 16 Mar, 2018 7 commits
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Thierry Reding authored
These callbacks allow the exporter to swap in and pin the backing storage for buffers as well as invalidate the cache in preparation for accessing the buffer from the CPU, and flush the cache and unpin the backing storage when the CPU is done modifying the buffer. Signed-off-by:Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
When allocating pages, map them with the DMA API in order to invalidate caches. This is the correct usage of the API and works just as well as faking up the SG table and using the dma_sync_sg_for_device() function. Signed-off-by: -
Thierry Reding authored
Rather than subclass the global atomic state to store the hub display clock and rate, create a private object and store this data in its state. Signed-off-by: -
Harry Wentland authored
Even though we default PRE_VEGA support to 'n' upstream in amd-staging we want to keep it enabled by default. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Rex Zhu authored
Refine commit f49e9bac ("drm/amd/pp: Get and save Rv smu version") Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Shirish S authored
This patch fixes static checker warning caused by "36cc549d: "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Clark Zheng authored
bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on. Signed-off-by:
Clark Zheng <clark.zheng@amd.com> Reviewed-by:
Tony Cheng <tony.cheng@amd.com> Acked-by:
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- 15 Mar, 2018 14 commits
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Andrey Grodzovsky authored
and amdgpu_bo_create_reserved. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Thierry Reding authored
Instead of relying on the tiling attached to a buffer object, make sure to set the proper tiling for linear buffers. Signed-off-by: -
Thierry Reding authored
Pass the list of valid format modifiers to planes upon initialization and implement the ->format_mod_supported() callback so that userspace can query for the valid combinations of formats and modifiers. Signed-off-by: -
Michel Dänzer authored
Turning off the sink in this case causes various issues, because userspace expects it to stay on until it turns it off explicitly. Instead, turn the sink off and back on when a display is connected again. This dance seems necessary for link training to work correctly. Bugzilla: https://bugs.freedesktop.org/105308 Cc: stable@vger.kernel.org Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Rex Zhu authored
Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Rex Zhu authored
hw ip smu8 was used on CZ/ST, so use smu8 as the prefix of the function/struct name in powerplay. Reviewed-by:
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Rex Zhu authored
Removes unneeded void * casts for the following pointers: hwmgr->backend hwmgr->smu_backend Reviewed-by:
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Rex Zhu authored
1. delete cz_clockpowergating.c/.h files 2. mark uvd/vce dpm/pg functions static Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
make it symmetric with amdgpu_ucode_init_bo in amd_powerplay.c refine the "commit b22558bb4ff8fc9fe925222f90297d7a03a5fb20" Reviewed-by:
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Rex Zhu authored
1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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