- 13 Apr, 2015 2 commits
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Ralf Baechle authored
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Ralf Baechle authored
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- 10 Apr, 2015 25 commits
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Markos Chandras authored
Commit 32098ec7 ("MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS") re-arranged the MIPS ASE detection code and also added the current cflags to the detection logic. However, this introduced a few bugs. First of all, the mips-cflags should not be quoted since that ends up being passed as a string to subsequent commands leading to broken detection from the cc-option-* tools. Moreover, in order to avoid duplicating the cflags-y because of how cc-option works, we rework the logic so we pass only those cflags which are needed by the selected ASE. Finally, fix some typos resulting in MSA not being detected correctly. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Fixes: Commit 32098ec7 ("MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS") Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9661/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
Set good default FPU flags (FR0) for O32 binaries similar to what the kernel does for the N64/N32 ones. This also fixes a regression introduced in commit 46490b57 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks") when MIPS_O32_FP64_SUPPORT is disabled. In that case, the mips_set_personality_fp() did not set the FPU mode at all because it assumed that the FPU mode was already set properly. That led to O32 userland problems. Signed-off-by:
Mans Rullgard <mans@mansr.com> Fixes: 46490b57 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks") Tested-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/9344/Signed-off-by:
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Rafał Miłecki authored
Since the day of adding this code it was broken. We were iterating over a wrong array and checking for wrong NVRAM entry. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/9654/Signed-off-by:
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Markos Chandras authored
A 64-bit build for Malta produces far too many build problems when SMP/CPS is selected. Moreover, there is currently no 64-bit product with SMP/CPS so we disable SMP/CPS when building for 64-bit until it is properly supported. Signed-off-by:
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Huacai Chen authored
We found that TLB mismatch not only happens after kernel resume, but also happens during snapshot restore. So move it to the beginning of swsusp_arch_suspend(). Signed-off-by:
Huacai Chen <chenhc@lemote.com> Cc: <stable@vger.kernel.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9621/Signed-off-by:
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Niklas Cassel authored
If we have an FPU, enroll ourselves in the FPU-full mask. Matching the MT_SMP and CMP implementations of smp_setup. Signed-off-by:
Niklas Cassel <niklass@axis.com> Cc: paul.burton@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8948/Signed-off-by:
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James Hogan authored
The lose_fpu() function only disables the FPU in CP0_Status.CU1 if the FPU is in use and MSA isn't enabled. This isn't necessarily a problem because KSTK_STATUS(current), the version of CP0_Status stored on the kernel stack on entry from user mode, does always get updated and gets restored when returning to user mode, but I don't think it was intended, and it is inconsistent with the case of only the FPU being in use. Sometimes leaving the FPU enabled may also mask kernel bugs where FPU operations are executed when the FPU might not be enabled. So lets disable the FPU in the MSA case too. Fixes: 33c771ba ("MIPS: save/disable MSA in lose_fpu") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9323/Signed-off-by:
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John Crispin authored
A driver was added in commit 5433acd8 ("MIPS: ralink: add illegal access driver") without the Kconfig section being added. Fix this by adding the symbol to the Kconfig file. Signed-off-by:
John Crispin <blogic@openwrt.org> Reported-by:
Paul Bolle <pebolle@tiscali.nl> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9299/Signed-off-by:
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John Crispin authored
A wrong symbol is referenced by commit 187c26dd ("MIPS: ralink: add rt2880 pci driver"). Fix this by changing it to the correct symbol. Signed-off-by:
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Adrien Schildknecht authored
The commit 21400f25 ("MIPS: BCM47XX: Make ssb init NVRAM instead of bcm47xx polling it") introduces a dependency to SSB_SFLASH but did not add it to the Kconfig. drivers/ssb/driver_mipscore.c:216:36: error: 'struct ssb_mipscore' has no member named 'sflash' struct ssb_sflash *sflash = &mcore->sflash; ^ drivers/ssb/driver_mipscore.c:249:12: error: dereferencing pointer to incomplete type if (sflash->present) { ^ Signed-off-by:
Adrien Schildknecht <adrien+dev@schischi.me> Cc: m@bues.ch Cc: zajec5@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9598/Signed-off-by:
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Markos Chandras authored
memsize denotes the amount of RAM we can access from kseg{0,1} and that should be up to 256M. In case the bootloader reports a value higher than that (perhaps reporting all the available RAM) it's best if we fix it ourselves and just warn the user about that. This is usually a problem with the bootloader and/or its environment. [ralf@linux-mips.org: Remove useless parens as suggested bei Sergei. Reformat long pr_warn statement to fit into 80 column limit.] Signed-off-by: -
Ralf Baechle authored
For a discussion, see http://patchwork.linux-mips.org/patch/9539/. This reverts commit 625c0a21.
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Ralf Baechle authored
This is no longer needed with the fixed, new and improved definition of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by:
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Ralf Baechle authored
Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by:
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Markos Chandras authored
Commit 6ebb496f("MIPS: kernel: entry.S: Add MIPS R6 related definitions") added the MIPSR6 definition but it did not update the ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro. Signed-off-by:
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Markos Chandras authored
Commit 5753762c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case. Signed-off-by:
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Markos Chandras authored
Commit 934c7923("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") added support for MIPS R6 cache flushes but it used the wrong base address register to perform the flushes so the same lines were flushed over and over. Moreover, replace the "addiu" instructions with LONG_ADDIU so the correct base address is calculated for 64-bit cores. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9384/Signed-off-by:
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Markos Chandras authored
Commit b0a668fb ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") added the mips r2-to-r6 emulator so an R2 userland can be executed on R6 kernels. This needed both build time and runtime support. The runtime support needed the "mipsr2emu" kernel parameter instead of the "mipsr2emul" listed in the Kconfig help message. Signed-off-by:
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Markos Chandras authored
When emulating a regular lh/lw/lhu/sh/sw we need to use the appropriate instruction if we are in EVA mode. This is necessary for userspace applications which trigger alignment exceptions. In such case, the userspace load/store instruction needs to be emulated with the correct eva/non-eva instruction by the kernel emulator. Signed-off-by:
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Markos Chandras authored
It's best to surround such complex macros with do {} while statements so they can appear as independent logical blocks when used within other control blocks. Signed-off-by: -
Markos Chandras authored
Commit c1771216 ("MIPS: kernel: unaligned: Handle unaligned accesses for EVA") allowed unaligned accesses to be emulated for EVA. However, when emulating regular load/store unaligned accesses, we need to use the appropriate "address space" instructions for that. Previously, an unaligned load/store instruction in kernel space would have used the corresponding EVA instructions to emulate it which led to segmentation faults because of the address translation that happens with EVA instructions. This is now fixed by using the EVA instruction only when emulating EVA unaligned accesses. Signed-off-by:
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Markos Chandras authored
Introduce new macros for kernel load/store variants which will be used to perform regular kernel space load/store operations in EVA mode. Signed-off-by:
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Ganesan Ramalingam authored
Update to the SATA PHY initialization. This is needed for SATA detection to succeed in all configurations. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8886/Signed-off-by:
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Aaro Koskinen authored
Fix PCI interrupt mapping for DSR1000N. This will get the PCI slot interrupts working. The mapping is based on D-Link GPL tarball. Signed-off-by:
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Alexander Sverdlin authored
udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon platforms because these operations are called from PCI_OP_READ() and PCI_OP_WRITE() under raw_spin_lock_irqsave(). Signed-off-by:
Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney@cavium.com> Cc: Rob Herring <robh@kernel.org> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Masanari Iida <standby24x7@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Mathias <mathias.rulf@nokia.com> Patchwork: https://patchwork.linux-mips.org/patch/9576/Signed-off-by:
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- 08 Apr, 2015 3 commits
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Florian Fainelli authored
Broadcom BCM63xx DSL SoCs utilize BMIPS CPUs, and as such are required to perform a read-ahead cache flush after a DMA transfer. Utilize asm/bmips.h to provide a plat_post_dma_flush_hook, and mach-generic/dma-coherence.h for everything else. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/9726/Signed-off-by:
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Florian Fainelli authored
Instead of having platforms to copy the entirety of mach-generic/dma-coherence.h, check whether these platforms have already defined a plat_post_dma_flush hook, and if not, provide an inline stub. Signed-off-by:
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Florian Fainelli authored
arch/mips/include/asm/mach-bmips/dma-coherence.h contains the plat_post_dma_flush implementation which is not specific to mach-bmips, but required for all BMIPS-based systems. Move plat_post_dma_flush to arch/mips/include/asm/bmips.h, rename it to bmips_post_dma_flush such that other platforms like bcm63xx can utilize it. Signed-off-by:
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- 07 Apr, 2015 10 commits
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Ralf Baechle authored
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Ralf Baechle authored
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Ralf Baechle authored
Introduced in 34c2f668 (MIPS: microMIPS: Add unaligned access support.) Signed-off-by:
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Maciej W. Rozycki authored
Following the arrangement for processors that wire FPU exceptions to the FPE CPU exception handle the case where no FPU is in use -- which for DECstation systems will only ever happen when the "nofpu" kernel option has been used -- do not register the FPU interrupt in such a case either. Signed-off-by:
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Maciej W. Rozycki authored
Implement a cheap way to count FPU interrupts for R2k/R3k DECstation systems. Do this manually in handcoded assembly, rather than calling `kstat_incr_irq_this_cpu' that would require setting up a stack frame and a lot of redirection. This is not going to be a problem because the FPU interrupt is local to the CPU and also there is one CPU only anyway. So at bootstrap determine the address of the correct location within `struct irq_desc', and then only refer to it directly in the interrupt handler. Signed-off-by:
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Maciej W. Rozycki authored
Factor out FPU feature probing, mainly to remove code duplication from `fpu_disable'. No functional change although shuffle some code to avoid forward references. Signed-off-by:
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Maciej W. Rozycki authored
Define the central place the default FCSR value is set from, initialised in `cpu_probe'. Determine the FCSR mask applied to values written to the register with CTC1 in the full emulation mode and via ptrace(2), according to the ISA level of processor hardware or the writability of bits 31:18 if actual FPU hardware is used. Software may rely on FCSR bits whose functions our emulator does not implement, so it should not allow them to be set or software may get confused. For ptrace(2) it's just sanity. [ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.] Signed-off-by:
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Maciej W. Rozycki authored
The ABS.fmt and NEG.fmt instructions have been specified as arithmetic in the MIPS architecture, which in particular implies handling NaN data in the usual way with qNaN bit patterns propagated unchanged and sNaN bit patterns signalling the usual IEEE 754 Invalid Operation exception and quieted by default. A series of changes applied over time to our implementation: c5033d78 [MIPS] ieee754[sd]p_neg workaround cea2be44 MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands has led to the current situation where the sign bit is updated according to the operation requested even for NaN inputs. This is according to these commits a workaround so that broken binaries produced by GCC disregarding the properties of these instructions have a chance to work. For sNaN inputs this remains within IEEE Std 754 as the standard leaves the choice of output qNaN bit patterns produced under the default Invalid Operation exception handling for individual sNaN input bit patterns to implementer's discretion, even though it still recommends as much NaN input information to be preserved in NaN outputs. For qNaN inputs however it violates the standard as it requires a qNaN input bit patterns to propagate unchanged to output. This is also unlike real MIPS FPU hardware behaves where sNaN and/or qNaN processing has been fully implemented with no Unimplemented Operation exception signalled. Such hardware propagates any input qNaN bit pattern unchanged. It also quiets any input sNaN bit pattern in an implementer-specific manner, for example the MIPS 74Kf processor returns the default qNaN pattern with the sign bit always clear and the Broadcom SB-1 and BMIPS5000 processors propagate the input sNaN bit pattern with the sign bit unchanged and the quiet bit first cleared in the trailing significand field and then the next lower bit set if clearing the quiet bit left the field with no other bit set. Especially the latter observation indicates the limited usefulness of the workaround as it will cover many hardware configurations, but not all of them, only making it harder to discover such broken binaries that need to be recompiled with GCC told to avoid the use of ABS.fmt and NEG.fmt instructions where non-arithmetic semantics is required by the algorithm used. Revert the damage done by the series of changes then, and take the opportunity to simplify implementation by calling `ieee754dp_sub' and `ieee754dp_add' as required and also the rounding mode set towards -Inf temporarily so that the sign of 0 is correctly handled. Signed-off-by:
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Maciej W. Rozycki authored
Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly. For completeness define FIR.UFRP too. Signed-off-by:
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Maciej W. Rozycki authored
Implement the FCCR, FEXR and FENR "shadow" FPU registers for the architecture levels that include them, for the CFC1 and CTC1 instructions in the full emulation mode. For completeness add macros for the CP1 UFR and UNFR registers too, no actual implementation though. Signed-off-by:
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