- 04 Apr, 2013 31 commits
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Laxman Dewangan authored
NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the following changes which makes incompatible with previous hardware: - Single clock source to I2C controller. - Interrupt support for per packet transfer. Add DT entry for I2C controllers and make it compatible with "nvidia,tegra114-i2c". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed location of status property for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma". Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA controller driver as in Tegra114, the global pause also clock gate the DMA register and hence it iw not possible to write the DMA register with global pause. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed DT node order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Andrew Chew authored
This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Andrew Chew authored
We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: Andrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Rhyland Klein authored
Dalmore has a built-in eMMC device and a user-accessible SD card slot. Add device tree nodes to enable these. Based on changes by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> [swarren: added commit description, fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Pritesh Raithatha authored
This patch adds in the SDHCI nodes for the busses supported on Tegra114 boards. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> [Rhyland added clk refs to & reordered sdhci nodes and removed spaces] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [swarren: fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Pritesh Raithatha authored
This change adds the default pinctrl nodes for the Dalmore Tegra114 platform. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> [Rhyland added patch description] Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> [swarren: fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Remove white-space from empty line; triggers checkpatch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Thierry Reding authored
By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Thierry Reding authored
The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Yen Lin authored
The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
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Stephen Warren authored
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- 03 Apr, 2013 7 commits
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Joseph Lo authored
After the patch series for system suspending support, tegra_idle_lp2_last() no longer uses its parameters cpu_on_time or cpu_off_time, so remove them. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Adding suspend to RAM support for Tegra platform. There are three suspend mode for Tegra. The difference were below. * LP2: CPU voltage off * LP1: CPU voltage off, DRAM in self-refresh * LP0: CPU + Core voltage off, DRAM in self-refresh After this patch, the LP2 suspend mode will be supported. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The PMC mostly controls the entry and exit of the system from different sleep modes. Different platform or system may have different configurations. The power management configurations of PMC is represented as some properties. The system needs to define the properties when the system supports deep sleep mode (i.e. suspend). Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Add the wake up handling for legacy irq controller, and using IRQCHIP_MASK_ON_SUSPEND for wake irq handling. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
This patch add the gpio wakeup source handling for the Tegra platform. It was be done by enabling the irq for the gpio in the gpio controller and enabling the bank irq of the gpio in the Tegra legacy irq controller when the system going to suspend. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The CPU power timer set up function was related to PMC register. Now moving it to PMC driver. And it also help to clean up the PM related code later. The timer was calculated based on the input clock of PMC. In this patch, we also get the clock from DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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- 02 Apr, 2013 2 commits
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Mike Turquette authored
Reentrancy into the clock framework is necessary for clock operations that result in nested calls to the clk api. A common example is a clock that is prepared via an i2c transaction, such as a clock inside of a discrete audio chip or a power management IC. The i2c subsystem itself will use the clk api resulting in a deadlock: clk_prepare(audio_clk) i2c_transfer(..) clk_prepare(i2c_controller_clk) The ability to reenter the clock framework prevents this deadlock. Other use cases exist such as allowing .set_rate callbacks to call clk_set_parent to achieve the best rate, or to save power in certain configurations. Yet another example is performing pinctrl operations from a clk_ops callback. Calls into the pinctrl subsystem may call clk_{un}prepare on an unrelated clock. Allowing for nested calls to reenter the clock framework enables both of these use cases. Reentrancy is implemented by two global pointers that track the owner currently holding a global lock. One pointer tracks the owner during sleepable, mutex-protected operations and the other one tracks the owner during non-interruptible, spinlock-protected operations. When the clk framework is entered we try to hold the global lock. If it is held we compare the current task against the current owner; a match implies a nested call and we reenter. If the values do not match then we block on the lock until it is released. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
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Mike Turquette authored
Create locking helpers for the global mutex and global spinlock. The definitions of these helpers will be expanded upon in the next patch which introduces reentrancy into the locking scheme. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
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