- 22 Aug, 2015 10 commits
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Paul Mackerras authored
When a vcore gets preempted, we put it on the preempted vcore list for the current CPU. The runner task then calls schedule() and comes back some time later and takes itself off the list. We need to be careful to lock the list that it was put onto, which may not be the list for the current CPU since the runner task may have moved to another CPU. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
Alexander Graf <agraf@suse.de>
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Paul Mackerras authored
This adds implementations for the H_CLEAR_REF (test and clear reference bit) and H_CLEAR_MOD (test and clear changed bit) hypercalls. When clearing the reference or change bit in the guest view of the HPTE, we also have to clear it in the real HPTE so that we can detect future references or changes. When we do so, we transfer the R or C bit value to the rmap entry for the underlying host page so that kvm_age_hva_hv(), kvm_test_age_hva_hv() and kvmppc_hv_get_dirty_log() know that the page has been referenced and/or changed. These hypercalls are not used by Linux guests. These implementations have been tested using a FreeBSD guest. Signed-off-by:
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Paul Mackerras authored
This fixes a bug in the tracking of pages that get modified by the guest. If the guest creates a large-page HPTE, writes to memory somewhere within the large page, and then removes the HPTE, we only record the modified state for the first normal page within the large page, when in fact the guest might have modified some other normal page within the large page. To fix this we use some unused bits in the rmap entry to record the order (log base 2) of the size of the page that was modified, when removing an HPTE. Then in kvm_test_clear_dirty_npages() we use that order to return the correct number of modified pages. The same thing could in principle happen when removing a HPTE at the host's request, i.e. when paging out a page, except that we never page out large pages, and the guest can only create large-page HPTEs if the guest RAM is backed by large pages. However, we also fix this case for the sake of future-proofing. The reference bit is also subject to the same loss of information. We don't make the same fix here for the reference bit because there isn't an interface for userspace to find out which pages the guest has referenced, whereas there is one for userspace to find out which pages the guest has modified. Because of this loss of information, the kvm_age_hva_hv() and kvm_test_age_hva_hv() functions might incorrectly say that a page has not been referenced when it has, but that doesn't matter greatly because we never page or swap out large pages. Signed-off-by:
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Paul Mackerras authored
The reference (R) and change (C) bits in a HPT entry can be set by hardware at any time up until the HPTE is invalidated and the TLB invalidation sequence has completed. This means that when removing a HPTE, we need to read the HPTE after the invalidation sequence has completed in order to obtain reliable values of R and C. The code in kvmppc_do_h_remove() used to do this. However, commit 6f22bd32 ("KVM: PPC: Book3S HV: Make HTAB code LE host aware") removed the read after invalidation as a side effect of other changes. This restores the read of the HPTE after invalidation. The user-visible effect of this bug would be that when migrating a guest, there is a small probability that a page modified by the guest and then unmapped by the guest might not get re-transmitted and thus the destination might end up with a stale copy of the page. Fixes: 6f22bd32Signed-off-by:
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Paul Mackerras authored
This builds on the ability to run more than one vcore on a physical core by using the micro-threading (split-core) modes of the POWER8 chip. Previously, only vcores from the same VM could be run together, and (on POWER8) only if they had just one thread per core. With the ability to split the core on guest entry and unsplit it on guest exit, we can run up to 8 vcpu threads from up to 4 different VMs, and we can run multiple vcores with 2 or 4 vcpus per vcore. Dynamic micro-threading is only available if the static configuration of the cores is whole-core mode (unsplit), and only on POWER8. To manage this, we introduce a new kvm_split_mode struct which is shared across all of the subcores in the core, with a pointer in the paca on each thread. In addition we extend the core_info struct to have information on each subcore. When deciding whether to add a vcore to the set already on the core, we now have two possibilities: (a) piggyback the vcore onto an existing subcore, or (b) start a new subcore. Currently, when any vcpu needs to exit the guest and switch to host virtual mode, we interrupt all the threads in all subcores and switch the core back to whole-core mode. It may be possible in future to allow some of the subcores to keep executing in the guest while subcore 0 switches to the host, but that is not implemented in this patch. This adds a module parameter called dynamic_mt_modes which controls which micro-threading (split-core) modes the code will consider, as a bitmap. In other words, if it is 0, no micro-threading mode is considered; if it is 2, only 2-way micro-threading is considered; if it is 4, only 4-way, and if it is 6, both 2-way and 4-way micro-threading mode will be considered. The default is 6. With this, we now have secondary threads which are the primary thread for their subcore and therefore need to do the MMU switch. These threads will need to be started even if they have no vcpu to run, so we use the vcore pointer in the PACA rather than the vcpu pointer to trigger them. It is now possible for thread 0 to find that an exit has been requested before it gets to switch the subcore state to the guest. In that case we haven't added the guest's timebase offset to the timebase, so we need to be careful not to subtract the offset in the guest exit path. In fact we just skip the whole path that switches back to host context, since we haven't switched to the guest context. Signed-off-by:
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Paul Mackerras authored
When running a virtual core of a guest that is configured with fewer threads per core than the physical cores have, the extra physical threads are currently unused. This makes it possible to use them to run one or more other virtual cores from the same guest when certain conditions are met. This applies on POWER7, and on POWER8 to guests with one thread per virtual core. (It doesn't apply to POWER8 guests with multiple threads per vcore because they require a 1-1 virtual to physical thread mapping in order to be able to use msgsndp and the TIR.) The idea is that we maintain a list of preempted vcores for each physical cpu (i.e. each core, since the host runs single-threaded). Then, when a vcore is about to run, it checks to see if there are any vcores on the list for its physical cpu that could be piggybacked onto this vcore's execution. If so, those additional vcores are put into state VCORE_PIGGYBACK and their runnable VCPU threads are started as well as the original vcore, which is called the master vcore. After the vcores have exited the guest, the extra ones are put back onto the preempted list if any of their VCPUs are still runnable and not idle. This means that vcpu->arch.ptid is no longer necessarily the same as the physical thread that the vcpu runs on. In order to make it easier for code that wants to send an IPI to know which CPU to target, we now store that in a new field in struct vcpu_arch, called thread_cpu. Reviewed-by:
David Gibson <david@gibson.dropbear.id.au> Tested-by:
Laurent Vivier <lvivier@redhat.com> Signed-off-by:
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Tudor Laurentiu authored
On this switch branch the regs initialization doesn't happen so add it. This was found with the help of a static code analysis tool. Signed-off-by:
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by:
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Thomas Huth authored
When compiling the KVM code for POWER with "make C=1", sparse complains about functions missing proper prototypes and a 64-bit constant missing the ULL prefix. Let's fix this by making the functions static or by including the proper header with the prototypes, and by appending a ULL prefix to the constant PPC_MPPE_ADDRESS_MASK. Signed-off-by:
Thomas Huth <thuth@redhat.com> Signed-off-by:
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Thomas Huth authored
Since the PPC970 support has been removed from the kvm-hv kernel module recently, we should also reflect this change in the help text of the corresponding Kconfig option. Signed-off-by:
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Tudor Laurentiu authored
This was signaled by a static code analysis tool. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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- 14 Aug, 2015 1 commit
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Andy Lutomirski authored
VMX encodes access rights differently from LAR, and the latter is most likely what x86 people think of when they think of "access rights". Rename them to avoid confusion. Cc: kvm@vger.kernel.org Signed-off-by:
Andy Lutomirski <luto@kernel.org> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- 13 Aug, 2015 1 commit
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Paolo Bonzini authored
Merge tag 'kvm-s390-next-20150812' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD KVM: s390: fix and feature for kvm/next (4.3) 1. error handling for irq routes 2. Gracefully handle STP time changes s390 supports a protocol for syncing different systems via the stp protocol that will steer the TOD clocks to keep all participating clocks below the round trip time between the system. In case of specific out of sync event Linux can opt-in to accept sync checks. This will result in non-monotonic jumps of the TOD clock, which Linux will correct via time offsets to keep the wall clock time monotonic. Now: KVM guests also base their time on the host TOD, so we need to fixup the offset for them as well.
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- 11 Aug, 2015 2 commits
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Wei Huang authored
According to AMD programmer's manual, AMD PERFCTRn is 64-bit MSR which, unlike Intel perf counters, doesn't require signed extension. This patch removes the unnecessary conversion in SVM vPMU code when PERFCTRn is being updated. Signed-off-by:
Wei Huang <wei@redhat.com> Reviewed-by:
Andrew Jones <drjones@redhat.com> Signed-off-by:
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Nicholas Krause authored
This fixes error handling in the function kvm_lapic_sync_from_vapic by checking if the call to kvm_read_guest_cached has returned a error code to signal to its caller the call to this function has failed and due to this we must immediately return to the caller of kvm_lapic_sync_from_vapic to avoid incorrectly call apic_set_tpc if a error has occurred here. Signed-off-by:
Nicholas Krause <xerofoify@gmail.com> Signed-off-by:
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- 07 Aug, 2015 1 commit
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Nicholas Krause authored
This fixes the assumption that kvm_set_irq_routing is always run successfully by instead making it equal to the variable r which we use for returning in the function kvm_arch_vm_ioctl instead of making r equal to zero when calling this particular function and incorrectly making the caller of kvm_arch_vm_ioctl think the function has run successfully. Signed-off-by:
Christian Borntraeger <borntraeger@de.ibm.com>
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- 05 Aug, 2015 10 commits
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Xiao Guangrong authored
The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by:
Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by:
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Xiao Guangrong authored
The #PF with PFEC.RSV = 1 is designed to speed MMIO emulation, however, it is possible that the RSV #PF is caused by real BUG by mis-configure shadow page table entries This patch enables full check for the zero bits on shadow page table entries (which includes not only bits reserved by the hardware, but also bits that will never be set in the SPTE), then dump the shadow page table hierarchy. Signed-off-by:
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Xiao Guangrong authored
We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by:
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Xiao Guangrong authored
We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check zero bits on shadow page tables The zero bits on sptes include not only reserved bits on hardware but also the bits that SPTEs willnever use. For example, shadow pages will never use GB pages unless the guest uses them too. Signed-off-by:
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Xiao Guangrong authored
Since shadow ept page tables and Intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by:
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Xiao Guangrong authored
Since softmmu & AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by:
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Xiao Guangrong authored
These two fields, rsvd_bits_mask and bad_mt_xwr, in "struct kvm_mmu" are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check host shadow page table entries as well Signed-off-by:
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Xiao Guangrong authored
FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by:
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Xiao Guangrong authored
We got the bug that qemu complained with "KVM: unknown exit, hardware reason 31" and KVM shown these info: [84245.284948] EPT: Misconfiguration. [84245.285056] EPT: GPA: 0xfeda848 [84245.285154] ept_misconfig_inspect_spte: spte 0x5eaef50107 level 4 [84245.285344] ept_misconfig_inspect_spte: spte 0x5f5fadc107 level 3 [84245.285532] ept_misconfig_inspect_spte: spte 0x5141d18107 level 2 [84245.285723] ept_misconfig_inspect_spte: spte 0x52e40dad77 level 1 This is because we got a mmio #PF and the handler see the mmio spte becomes normal (points to the ram page) However, this is valid after introducing fast mmio spte invalidation which increases the generation-number instead of zapping mmio sptes, a example is as follows: 1. QEMU drops mmio region by adding a new memslot 2. invalidate all mmio sptes 3. VCPU 0 VCPU 1 access the invalid mmio spte access the region originally was MMIO before set the spte to the normal ram map mmio #PF check the spte and see it becomes normal ram mapping !!! This patch fixes the bug just by dropping the check in mmio handler, it's good for backport. Full check will be introduced in later patches Reported-by:Pavel Shirshov <ru.pchel@gmail.com> Tested-by:
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Alex Williamson authored
The patch was munged on commit to re-order these tests resulting in excessive warnings when trying to do device assignment. Return to original ordering: https://lkml.org/lkml/2015/7/15/769 Fixes: 3e5d2fdc ("KVM: MTRR: simplify kvm_mtrr_get_guest_memory_type") Signed-off-by:
Alex Williamson <alex.williamson@redhat.com> Reviewed-by:
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- 04 Aug, 2015 1 commit
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Fan Zhang authored
If the host has STP enabled, the TOD of the host will be changed during synchronization phases. These are performed during a stop_machine() call. As the guest TOD is based on the host TOD, we have to make sure that: - no VCPU is in the SIE (implicitly guaranteed via stop_machine()) - manual guest TOD calculations are not affected "Epoch" is the guest TOD clock delta to the host TOD clock. We have to adjust that value during the STP synchronization and make sure that code that accesses the epoch won't get interrupted in between (via disabling preemption). Signed-off-by:
Fan Zhang <zhangfan@linux.vnet.ibm.com> Reviewed-by:
David Hildenbrand <dahi@linux.vnet.ibm.com> Reviewed-by:
Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by:
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- 30 Jul, 2015 2 commits
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Paolo Bonzini authored
The memory barriers are trying to protect against concurrent RCU-based interrupt injection, but the IRQ routing table is not valid at the time kvm->arch.vpic is written. Fix this by writing kvm->arch.vpic last. kvm_destroy_pic then need not set kvm->arch.vpic to NULL; modify it to take a struct kvm_pic* and reuse it if the IOAPIC creation fails. Signed-off-by: -
Paolo Bonzini authored
Signed-off-by:
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- 29 Jul, 2015 12 commits
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Paolo Bonzini authored
There is no smp_rmb matching the smp_wmb. shared_msr_update is called from hardware_enable, which in turn is called via on_each_cpu. on_each_cpu and must imply a read memory barrier (on x86 the rmb is achieved simply through asm volatile in native_apic_mem_write). Signed-off-by: -
Paolo Bonzini authored
This is another remnant of ia64 support. Signed-off-by: -
Paolo Bonzini authored
Merge tag 'kvm-s390-next-20150728' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into kvm-next KVM: s390: Fixes and features for kvm/next (4.3) 1. Rework logging infrastructure (s390dbf) to integrate feedback learned when debugging performance and test issues 2. Some cleanups and simplifications for CMMA handling 3. Fix gdb debugging and single stepping on some instructions 4. Error handling for storage key setup
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Christian Borntraeger authored
Depending on user space, some capabilities and vm attributes are enabled at runtime. Let's log those events and while we're at it, log querying the vm attributes as well. Signed-off-by: -
Christian Borntraeger authored
In addition to the per VM debug logs, let's provide a global one for KVM-wide events, like new guests or fatal errors. Signed-off-by:
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Christian Borntraeger authored
Use the default log level 3 for state changing and/or seldom events, use 4 for others. Also change some numbers from %x to %d and vice versa to match documentation. If hex, let's prepend the numbers with 0x. Signed-off-by:
Cornelia Huck <cornelia.huck@de.ibm.com>
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Christian Borntraeger authored
We do not use the exception logger, so the 2nd area is unused. Just have one area that is bigger (32 pages). At the same time we can limit the debug feature size to 7 longs, as the largest user has 3 parameters + string + boiler plate (vCPU, PSW mask, PSW addr) Signed-off-by:
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Christian Borntraeger authored
The old Documentation/s390/kvm.txt file is either outdated or described in Documentation/virtual/kvm/api.txt. Let's get rid of it. Signed-off-by:
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David Hildenbrand authored
This patch adds names for missing irq types to the trace events. In order to identify adapter irqs, the define is moved from interrupt.c to the other basic irq defines in uapi/linux/kvm.h. Acked-by:
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Christian Borntraeger authored
This reworks the debug logging for interrupt related logs. Several changes: - unify program int/irq - improve decoding (e.g. use mcic instead of parm64 for machine check injection) - remove useless interrupt type number (the name is enough) - rename "interrupt:" to "deliver:" as the other side is called "inject" - use log level 3 for state changing and/or seldom events (like machine checks, restart..) - use log level 4 for frequent events - use 0x prefix for hex numbers - add pfault done logging - move some tracing outside spinlock Signed-off-by:
Jens Freimann <jfrei@linux.vnet.ibm.com>
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Christian Borntraeger authored
We're not only interested in the address of the control block, but also in the requested subcommand and for the token subcommand, in the specified token address and masks. Suggested-by:
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David Hildenbrand authored
The "from user"/"from kernel" part of the log/trace messages is not always correct anymore and therefore not really helpful. Let's remove that part from the log + trace messages. For program interrupts, we can now move the logging/tracing part into the real injection function, as already done for the other injection functions. Reviewed-by:
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