- 11 Sep, 2018 22 commits
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David Francis authored
[Why] The i2c and aux engines are similar, and should be placed next to eachother for readability [How] Reorder the elements of the resource_pool struct Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo Li authored
[Why] Our implementation is functionally identical to DRM's Note that instead of checking if the provided id is 0, the helper follows through with the mode object search. However, It will still return NULL, since 0 is not a valid object id, and missed searches will return NULL. [How] Remove our implementation, and replace it with drm_atomic_helper_best_encoder. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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Hersen Wu authored
[why] AMD Stoney reference board, there are only 2 pipes (not include underlay), and 3 connectors. resource creation, only 2 I2C/AUX engines are created. Within dc_link_aux_transfer, when pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL. NULL point is referred later causing system crash. [how] each asic design has fixed number of ddc engines at hw side. for each ddc engine, create its i2x/aux engine at sw side. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Chiawen Huang authored
[Why] Enhance aux transition debugging information. [How] Added Aux request and reply event log. Signed-off-by:
Chiawen Huang <chiawen.huang@amd.com> Reviewed-by:
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Derek Lai authored
Some display need disconnect delay. Adding this parameter for future use Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Jun Lei authored
Although 4 unique register values exist for gamma modes, two are actually the same (the two RAMs) It’s not possible for caller to understand this HW specific behavior, so some parsing is necessary in driver Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Gary Kattan authored
[Why]Update Code to get DTN golden log check to pass for tests run after DAL217 tests. [How]Change how dcn10_log_hw_state function prints HW state info (CM_GAMUT_REMAP_Cx_Cx registers) when GAMUT REMAP is in bypass mode. Signed-off-by:
Gary Kattan <gary.kattan@amd.com> Reviewed-by:
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Eric Bernstein authored
[Why] For supporting DP YCbCr 4:2:0 output. [How] Update mod_build_vsc_infopacket to support Pixel Encoding/Colorimetry Format indication for VSC SDP rev5. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] We currently lock modeset by setting a boolean in dm. We want to lock Based on what DC tells us. [How] Build stream_updates and plane_update based on what changed. Then we call check_update_surfaces_for_stream() to get the update type We lock only if update_type is not fast Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
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Christian König authored
Otherwise we won't be able to use the AGP aperture. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Christian König authored
Start to use the old AGP aperture for system memory access. v2: Move that to amdgpu_ttm_alloc_gart Signed-off-by:
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Christian König authored
Helper to figure out the location of the AGP BAR. v2: fix a couple of bugs v3: correctly add one to vram_end Signed-off-by:
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Christian König authored
Correct sign extend the GMC addresses to 48bit. v2: sign extending turned out easier than thought. v3: clean up the defines and move them into amdgpu_gmc.h as well Signed-off-by:
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Christian König authored
Since we have a lot of FAQ on the VM state machine try to improve the documentation by adding functions for each state move. v2: fix typo in amdgpu_vm_bo_invalidated, use amdgpu_vm_bo_relocated in one more place as well. Signed-off-by: -
Christian König authored
Avoid unlocking a lock we never locked. Signed-off-by:
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Christian König authored
Allows us to avoid taking the spinlock in more places. Signed-off-by:
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Christian König authored
amdgpu_vm_bo_* functions should come much later. Signed-off-by:
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Evan Quan authored
For under voltage, negative value will be applied to voltage offset. Update the data type to cover this case. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Added vega20 overdrive support based on existing OD sysfs APIs. However, the OD logics are simplified on vega20. So, the behavior will be a little different and works only on some limited levels. V2: fix typo fix commit description revise error logs add support for clock OD V3: separate clock from voltage OD settings Signed-off-by:
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- 02 Sep, 2018 8 commits
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Alex Deucher authored
Vega20 does not appear to be affected by the same issue as vega10. Enable the full stolen memory handling on vega20. Reserve the appropriate size at init time to avoid display artifacts and then free it at the end of init once the new FB is up and running. Acked-by:
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Alex Deucher authored
vega12 does not appear to be affected by the same issue as vega10. Enable the full stolen memory handling on vega12. Reserve the appropriate size at init time to avoid display artifacts and then free it at the end of init once the new FB is up and running. Acked-by:
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Alex Deucher authored
Raven does not appear to be affected by the same issue as vega10. Enable the full stolen memory handling on Raven. Reserve the appropriate size at init time to avoid display artifacts and then free it at the end of init once the new FB is up and running. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106639Reviewed-by:
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Alex Deucher authored
No functional change, just rework it in order to adjust the behavior on a per asic level. The problem is that on vega10, something corrupts the lower 8 MB of vram on the second resume from S3. This does not seem to affect Raven, other gmc9 based asics need testing. Reviewed-by:
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Christian König authored
Add BOs to the idle state again and correctly clear the flag when new BOs are added. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
First step to fix the LRU corruption, we accidentially tried to move things on the LRU after dropping the lock. Signed-off-by:
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Christian König authored
Staring at the function for six hours, just to essentially move one line of code. The problem was that the first list_cut_position call could result in list2 pointing to la-la-land. Signed-off-by:
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Andrey Grodzovsky authored
This at least allows to fail any subsequent IOCTLs with -ENODEV after the device is gone. Still this operation is not supported yet in graphic mode and will lead at least to page faults and other issues. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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- 30 Aug, 2018 2 commits
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Christian König authored
This reverts commit a7f91061. Felix pointed out that we need to have the BOs mapped even before amdgpu_vm_update_directories is called. Signed-off-by:
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Christian König authored
Always try to put the GART away from where VRAM is. v2: correctly handle the 4GB limitation Signed-off-by:
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- 29 Aug, 2018 8 commits
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Alex Deucher authored
This caused a confusing error message, but there is functionally no problem since the default method is DIRECT. Reviewed-by:
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Amber Lin authored
Move some KFD-related (but used in amdgpu_drv.c) definitions from kfd_priv.h to kgd_kfd_interface.h so we don't need to include kfd_priv.h in amdgpu_drv.c. This fixes a build failure when AMDGPU is enabled but MMU_NOTIFIER is not. This patch also disables KFD-related module options when HSA_AMD is not enabled. v2: rebase (Alex) Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
kvmalloc_array uses __GFP_ZERO flag ensures that the returned address is zeroed already, memset it to zero again afterwards is unnecessary, and in this case buggy because we only clear the first entry. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Michel Dänzer authored
The first parameter of list_cut_position() must point to an initialized list. Noticed thanks to KASAN pointing out something's fishy here. Fixes: "drm/ttm: add bulk move function on LRU" Reviewed-by:
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Christian König authored
Instead of the larger one use the smaller hole in the MC address space for the GART mappings. Signed-off-by:
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Michel Dänzer authored
This reverts commit 31625ccae4464b61ec8cdb9740df848bbc857a5b. It triggered various badness on my development machine when running the piglit gpu profile with radeonsi on Bonaire, looks like memory corruption due to insufficiently protected list manipulations. Signed-off-by:
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Christian König authored
Most of the time we only need to know if the BO has a valid GMC addr. Signed-off-by:
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Christian König authored
Further separate GART and GTT domain. Signed-off-by:
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