1. 05 Jul, 2020 3 commits
    • Linus Torvalds's avatar
      Merge tag 'mips_fixes_5.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux · 45a5ac7a
      Linus Torvalds authored
      Pull MIPS fixes from Thomas Bogendoerfer:
      
       - fix for missing hazard barrier
      
       - DT fix for ingenic
      
       - DT fix of GPHY names for lantiq
      
       - fix usage of smp_processor_id() while preemption is enabled
      
      * tag 'mips_fixes_5.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
        MIPS: Do not use smp_processor_id() in preemptible code
        MIPS: Add missing EHB in mtc0 -> mfc0 sequence for DSPen
        MIPS: ingenic: gcw0: Fix HP detection GPIO.
        MIPS: lantiq: xway: sysctrl: fix the GPHY clock alias names
      45a5ac7a
    • Xingxing Su's avatar
      MIPS: Do not use smp_processor_id() in preemptible code · 5868347a
      Xingxing Su authored
      Use preempt_disable() to fix the following bug under CONFIG_DEBUG_PREEMPT.
      
      [   21.915305] BUG: using smp_processor_id() in preemptible [00000000] code: qemu-system-mip/1056
      [   21.923996] caller is do_ri+0x1d4/0x690
      [   21.927921] CPU: 0 PID: 1056 Comm: qemu-system-mip Not tainted 5.8.0-rc2 #3
      [   21.934913] Stack : 0000000000000001 ffffffff81370000 ffffffff8071cd60 a80f926d5ac95694
      [   21.942984]         a80f926d5ac95694 0000000000000000 98000007f0043c88 ffffffff80f2fe40
      [   21.951054]         0000000000000000 0000000000000000 0000000000000001 0000000000000000
      [   21.959123]         ffffffff802d60cc 98000007f0043dd8 ffffffff81f4b1e8 ffffffff81f60000
      [   21.967192]         ffffffff81f60000 ffffffff80fe0000 ffff000000000000 0000000000000000
      [   21.975261]         fffffffff500cce1 0000000000000001 0000000000000002 0000000000000000
      [   21.983331]         ffffffff80fe1a40 0000000000000006 ffffffff8077f940 0000000000000000
      [   21.991401]         ffffffff81460000 98000007f0040000 98000007f0043c80 000000fffba8cf20
      [   21.999471]         ffffffff8071cd60 0000000000000000 0000000000000000 0000000000000000
      [   22.007541]         0000000000000000 0000000000000000 ffffffff80212ab4 a80f926d5ac95694
      [   22.015610]         ...
      [   22.018086] Call Trace:
      [   22.020562] [<ffffffff80212ab4>] show_stack+0xa4/0x138
      [   22.025732] [<ffffffff8071cd60>] dump_stack+0xf0/0x150
      [   22.030903] [<ffffffff80c73f5c>] check_preemption_disabled+0xf4/0x100
      [   22.037375] [<ffffffff80213b84>] do_ri+0x1d4/0x690
      [   22.042198] [<ffffffff8020b828>] handle_ri_int+0x44/0x5c
      [   24.359386] BUG: using smp_processor_id() in preemptible [00000000] code: qemu-system-mip/1072
      [   24.368204] caller is do_ri+0x1a8/0x690
      [   24.372169] CPU: 4 PID: 1072 Comm: qemu-system-mip Not tainted 5.8.0-rc2 #3
      [   24.379170] Stack : 0000000000000001 ffffffff81370000 ffffffff8071cd60 a80f926d5ac95694
      [   24.387246]         a80f926d5ac95694 0000000000000000 98001007ef06bc88 ffffffff80f2fe40
      [   24.395318]         0000000000000000 0000000000000000 0000000000000001 0000000000000000
      [   24.403389]         ffffffff802d60cc 98001007ef06bdd8 ffffffff81f4b818 ffffffff81f60000
      [   24.411461]         ffffffff81f60000 ffffffff80fe0000 ffff000000000000 0000000000000000
      [   24.419533]         fffffffff500cce1 0000000000000001 0000000000000002 0000000000000000
      [   24.427603]         ffffffff80fe0000 0000000000000006 ffffffff8077f940 0000000000000020
      [   24.435673]         ffffffff81460020 98001007ef068000 98001007ef06bc80 000000fffbbbb370
      [   24.443745]         ffffffff8071cd60 0000000000000000 0000000000000000 0000000000000000
      [   24.451816]         0000000000000000 0000000000000000 ffffffff80212ab4 a80f926d5ac95694
      [   24.459887]         ...
      [   24.462367] Call Trace:
      [   24.464846] [<ffffffff80212ab4>] show_stack+0xa4/0x138
      [   24.470029] [<ffffffff8071cd60>] dump_stack+0xf0/0x150
      [   24.475208] [<ffffffff80c73f5c>] check_preemption_disabled+0xf4/0x100
      [   24.481682] [<ffffffff80213b58>] do_ri+0x1a8/0x690
      [   24.486509] [<ffffffff8020b828>] handle_ri_int+0x44/0x5c
      Signed-off-by: default avatarXingxing Su <suxingxing@loongson.cn>
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
      5868347a
    • Hauke Mehrtens's avatar
      MIPS: Add missing EHB in mtc0 -> mfc0 sequence for DSPen · fcec538e
      Hauke Mehrtens authored
      This resolves the hazard between the mtc0 in the change_c0_status() and
      the mfc0 in configure_exception_vector(). Without resolving this hazard
      configure_exception_vector() could read an old value and would restore
      this old value again. This would revert the changes change_c0_status()
      did. I checked this by printing out the read_c0_status() at the end of
      per_cpu_trap_init() and the ST0_MX is not set without this patch.
      
      The hazard is documented in the MIPS Architecture Reference Manual Vol.
      III: MIPS32/microMIPS32 Privileged Resource Architecture (MD00088), rev
      6.03 table 8.1 which includes:
      
         Producer | Consumer | Hazard
        ----------|----------|----------------------------
         mtc0     | mfc0     | any coprocessor 0 register
      
      I saw this hazard on an Atheros AR9344 rev 2 SoC with a MIPS 74Kc CPU.
      There the change_c0_status() function would activate the DSPen by
      setting ST0_MX in the c0_status register. This was reverted and then the
      system got a DSP exception when the DSP registers were saved in
      save_dsp() in the first process switch. The crash looks like this:
      
      [    0.089999] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
      [    0.097796] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
      [    0.107070] Kernel panic - not syncing: Unexpected DSP exception
      [    0.113470] Rebooting in 1 seconds..
      
      We saw this problem in OpenWrt only on the MIPS 74Kc based Atheros SoCs,
      not on the 24Kc based SoCs. We only saw it with kernel 5.4 not with
      kernel 4.19, in addition we had to use GCC 8.4 or 9.X, with GCC 8.3 it
      did not happen.
      
      In the kernel I bisected this problem to commit 9012d011 ("compiler:
      allow all arches to enable CONFIG_OPTIMIZE_INLINING"), but when this was
      reverted it also happened after commit 172dcd93 ("MIPS: Always
      allocate exception vector for MIPSr2+").
      
      Commit 0b24cae4 ("MIPS: Add missing EHB in mtc0 -> mfc0 sequence.")
      does similar changes to a different file. I am not sure if there are
      more places affected by this problem.
      Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
      fcec538e
  2. 04 Jul, 2020 7 commits
  3. 03 Jul, 2020 29 commits
  4. 02 Jul, 2020 1 commit