- 20 Mar, 2019 8 commits
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Ville Syrjälä authored
To allow unsetting .is_mobile for the desktop variant of PNV fix up the cdclk code to select the mobile HPLLVCO register for both PNV variants. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318165633.28924-5-ville.syrjala@linux.intel.comReviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Ville Syrjälä authored
We want to allow the desktop PNV to not have .is_mobile set. To that end let's add a small helper to determine if the platform has the ASLE interrupt (or equivalent). Supposdely both PNV variants have it. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
Add a small helper to determine if we have the panel power sequencer or not. We'll make PNV an exceptional case so that we can unset .is_mobile for the desktop variant. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
Make the code self-documenting by introducing i9xx_has_pfit(). Also make PNV an exceptional case so that we can unset .is_mobile for the desktop variant. v2: s/gen4/gen>=4/ (Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
g33/i964g/g45 are the exceptional cases when it comes to the swizzle detection. Let's reorder the code to handle them first and let everything else be handled by the else branch. This allows us to unset .is_mobile for the desktop PNV variant (which supposedly must follow the "mobile" path here). Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
Exercise acquiring and releasing forcewake around register reads. In order to read a register behind a GT powerwell, we need to instruct that powerwell to wake up using a forcewake. When we no longer require the GT powerwell, we tell the GT to release our forcewake. Inside the forcewake, the register read should work but outside it should just return garbage, 0 being the most common garbage. Thus we can detect when we are inside and outside of the forcewake with just a simple register read, and so can verify that the GT powerwell is released when we say so. v2: Picking the right forcewaked register to return 0 outside of forcewake is an art. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
If a test fails, we quite often mark the device as wedged. Provide the stub functions so that we can wedge the mock device, and avoid exploding on test failures. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109981Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190319214233.25498-3-chris@chris-wilson.co.uk
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Joonas Lahtinen authored
Signed-off-by:Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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- 19 Mar, 2019 23 commits
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Anusha Srivatsa authored
Comet Lake PCH is based off of Cannon Point(CNP). Add PCI ID for Comet Lake PCH. v2: Code cleanup (DK) v3: Comment cleanup (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318200133.9666-2-anusha.srivatsa@intel.com
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Anusha Srivatsa authored
Comet Lake is a Intel Processor containing Gen9 Intel HD Graphics. This patch adds the initial set of PCI IDs. Comet Lake comes off of Coffee Lake - adding the IDs to Coffee Lake ID list. More support and features will be in the patches that follow. v2: Split IDs according to GT. (Rodrigo) v3: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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José Roberto de Souza authored
There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now lets workaround the issue by cleaning PSR_CTL before enable PSR2. v2: - Updated commit description and comment to state that it may be a DMC firmware issue (Rodrigo) - No need to RMW, let's write 0 to PSR_CTL(Dhinakaran) Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190314230113.6571-1-jose.souza@intel.com
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Ville Syrjälä authored
Make things look a bit nicer by passing dev_priv to intel_is_dual_link_lvds(). Signed-off-by:
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Ville Syrjälä authored
Pass dev_priv to intel_get_lvds_encoder() and polish the implementation a bit. Signed-off-by:
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Ville Syrjälä authored
Sprinkle some curly braces in accordance with the coding style. Signed-off-by:
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Ville Syrjälä authored
Rather than try to maintain some magic relationship between the link rates and the index into the wrpll params array let's just store the link rate in the array itself. Much less fragile. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com>
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Ville Syrjälä authored
We already have the code to calculate the WRPLL output clock from the register values, but for some reason we're only using it for HDMI and not DP. Throw out the inflexible DP DPLL table lookup and just call the HDMI code which decodes the actual register values. Signed-off-by:
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Ville Syrjälä authored
The readout code thinks that kdiv of 3 is 4. Fix it. Signed-off-by:
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Ville Syrjälä authored
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by:
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Ville Syrjälä authored
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by:
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Ville Syrjälä authored
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by:
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Ville Syrjälä authored
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by:
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Ville Syrjälä authored
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by:
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Ville Syrjälä authored
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by:
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Ville Syrjälä authored
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by:
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Ville Syrjälä authored
Simplify the calling convention of the skl dpll funcs by plumbing the crtc state deeper. Signed-off-by:
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Ville Syrjälä authored
Passing both crtc and its state is redundant. Pass just the state. Signed-off-by:
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Ville Syrjälä authored
Passing both crtc and its state is redundant. Pass just the state. Signed-off-by:
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Chris Wilson authored
For virtual engines, we need to keep the HW context alive while it remains in use. For regular HW contexts, they are created and kept alive until the end of the GEM context. For simplicity, generalise the requirements and keep an active reference to each HW context. Signed-off-by:
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Chris Wilson authored
On unpinning the intel_context, we remove it from the active list inside the GEM context. This list is supposed to be guarded by the GEM context mutex, so remember to take it! Fixes: 7e3d9a59 ("drm/i915: Track active engines within a context") Signed-off-by:
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Jani Nikula authored
We've been free of deprecated drmP.h includes for a while, but one crept in. Fend it off. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318160409.27648-1-jani.nikula@intel.com
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Jani Nikula authored
We no longer allow mixed C99 and kernel types, and the preference is to use kernel types exclusively. Fix the C99 types that have crept in since the mass conversion. No functional changes. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: Kevin Strasser <kevin.strasser@intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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- 18 Mar, 2019 9 commits
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Chris Wilson authored
As the final request on a ring may hold the reference to this ring (via retiring the last pinned context), we may find ourselves chasing a dangling pointer on completion of the list. A quick solution is to hold a reference to the ring itself as we retire along it so that we only free it after we stop dereferencing it. Signed-off-by:
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Chris Wilson authored
If we use the STORE_DATA_INDEX function we can use a fixed offset and avoid having to lookup up the engine HWS address. A step closer to being able to emit the final breadcrumb during request_add rather than later in the submission interrupt handler. Signed-off-by:
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Ville Syrjälä authored
We're currently leaving the CUS enabled if we disable the master plane directly after scanning out NV12. Could perhaps cause the selected slave plane to misbehave if we try to use it for scanning out something non-NV12? Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110032
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Ville Syrjälä authored
We must remember to actually enable the post CSC gamma if we expect the legacy LUT to work. Seems to fix NV12 crc tests on the SDR planes. Curiously we apparently managed to get 100% match for the HDR planes even without chopping off the low bits. Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Joonas Lahtinen authored
Merge tag 'topic/hdr-formats-2019-03-13' of git://anongit.freedesktop.org/drm/drm-misc into drm-intel-next-queued Add support for floating point half-width formats. Signed-off-by:
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Jani Nikula authored
Slightly verbose, but does away with hand rolled shifts. Ties the field values with the mask defining the field. Unfortunately we have to make a local copy of FIELD_PREP() to evaluate to a integer constant expression. But with this, we can ensure the mask is non-zero, power of 2, fits u32, and the value fits the mask (when the value is a constant expression). Convert power sequencer registers as an example. v4: - rebase v3: - rename the macro to REG_FIELD_PREP to avoid underscore prefix and to be in line with kernel macros (Chris) - rename power of 2 check macro (Chris) v2: - add build-time checks with BUILD_BUG_ON_ZERO() - rename to just _FIELD() due to regmap.h REG_FIELD() clash Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
bitfield.h defines FIELD_GET() and FIELD_PREP() macros to access bitfields using the mask alone, with no need for separate shift. Indeed, the shift is redundant. We define REG_FIELD_GET() and REG_FIELD_PREP() wrappers for the above, in part to force u32 and for consistency with REG_BIT() and REG_GENMASK(), but also as we'll need to redefine REG_FIELD_PREP() in follow-up work to make it produce integer constant expressions. For the most part, REG_FIELD_GET() is shorter than masking followed by shift, and arguably has more clarity. REG_FIELD_PREP() can get more verbose than simply shifting in place, but it does provide masking to ensure we don't overflow the mask, something we usually don't bother with currently. Convert power sequencer registers as an example. v3: - temp variable removal (Chris) - rebase v2: - Add the REG_FIELD_GET() and REG_FIELD_PREP() wrappers to use them consistently from the start. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Introduce REG_BIT(n) to define register bits and REG_GENMASK(h, l) to define register bitfield masks. We define the above as wrappers to BIT() and GENMASK() respectively to force u32 type to go with our register size, and to add compile time checks on the bit numbers. The intention is that these are easier to get right and review against the spec than hand rolled masks. Convert power sequencer registers as an example. v4: - rebase v3: - rename macros to REG_BIT() and REG_GENMASK() to avoid underscore prefix and to be in line with kernel macros (Chris) - add compile time checks (Mika) v2: - rename macros to just _BIT() and _MASK() to reduce verbosity Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
We only need to acquire a wakeref for ourselves for a few operations, as most either already acquire their own wakeref or imply a wakeref. In particular, it is i915_gem_set_wedged() that needed us to present it with a wakeref, which is incongruous with its "use anywhere" ability. Suggested-by:
"Yokoyama, Caz" <caz.yokoyama@intel.com> Signed-off-by:
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