- 12 Jul, 2019 7 commits
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Stephen Boyd authored
Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', 'clk-sprd' and 'clk-at91' into clk-next - Support for CPU clks on Raspberry Pi devices - Slow clk support for AT91 SAM9X60 SoCs * clk-rpi-cpufreq: clk: raspberrypi: register platform device for raspberrypi-cpufreq firmware: raspberrypi: register clk device clk: bcm283x: add driver interfacing with Raspberry Pi's firmware clk: bcm2835: remove pllb * clk-tegra: clk: tegra: Do not enable PLL_RE_VCO on Tegra210 clk: tegra: Warn if an enabled PLL is in IDDQ clk: tegra: Do not warn unnecessarily clk: tegra210: fix PLLU and PLLU_OUT1 * clk-simplify-provider.h: clk: consoldiate the __clk_get_hw() declarations clk: Unexport __clk_of_table clk: Remove ifdef for COMMON_CLK in clk-provider.h * clk-sprd: clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: sprd: Check error only for devm_regmap_init_mmio() clk: sprd: Switch from of_iomap() to devm_ioremap_resource() * clk-at91: clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: at91: sckc: add support for SAM9X60 dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller clk: at91: sckc: add support to specify registers bit offsets clk: at91: sckc: sama5d4 has no bypass support
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Stephen Boyd authored
- Add a 'clk_parent' file in clk debugfs - Remove dead code in various clk drivers * clk-debugfs: clk: Add clk_parent entry in debugfs * clk-unused: clk: qcom: Fix -Wunused-const-variable clk: mmp: frac: Remove set but not used variable 'prev_rate' clk: ti: Remove unused functions clk: mediatek: mt8516: Remove unused variable * clk-refactor: clk: clk-cdce706: simplify getting the adapter of a client clk: Simplify clk_core_can_round() * clk-qoriq: clk: qoriq: add support for lx2160a
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Stephen Boyd authored
- Add a clk_bulk_get_optional() API (with devm too) - Support for Marvell 98DX1135 SoCs * clk-bulk-optional: clk: Document some devm_clk_bulk*() APIs clk: Add devm_clk_bulk_get_optional() function clk: Add clk_bulk_get_optional() function * clk-kirkwood: clk: kirkwood: Add support for MV98DX1135 dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock * clk-socfpga: clk: socfpga: stratix10: fix divider entry for the emac clocks clk: socfpga: stratix10: add additional clocks needed for the NAND IP * clk-docs: clk: Grammar missing "and", Spelling s/statisfied/satisfied/
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Stephen Boyd authored
* clk-ti: clk: ti: Use int to check return value from of_property_count_elems_of_size() firmware: ti_sci: extend clock identifiers from u8 to u32 clk: keystone: sci-clk: extend clock IDs to 32 bits clk: keystone: sci-clk: probe clocks from DT instead of firmware clk: keystone: sci-clk: split out the fw clock parsing to own function clk: keystone: sci-clk: cut down the clock name length * clk-samsung: clk: samsung: Add bus clock for GPU/G3D on Exynos4412 clk: samsung: add new clocks for DMC for Exynos5422 SoC clk: samsung: add BPLL rate table for Exynos 5422 SoC clk: samsung: add needed IDs for DMC clocks in Exynos5420 clk: samsung: exynos5433: Use of_clk_get_parent_count() * clk-imx: (38 commits) clk: imx8mq: Keep uart clocks on during system boot clk: imx: Remove __init for imx_register_uart_clocks() API clk: imx6q: fix section mismatch warning clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap() clk: imx8mq: Use imx_check_clocks() API directly clk: imx: Remove __init for imx_check_clocks() API clk: imx6sll: Switch to clk_hw based API clk: imx7d: Switch to clk_hw based API clk: imx6ul: Switch to clk_hw based API clk: imx6sx: Switch to clk_hw based API clk: imx6q: Switch to clk_hw based API clk: imx6sl: Switch to clk_hw based API clk: imx: Switch wrappers to clk_hw based API clk: imx: clk-fixup-mux: Switch to clk_hw based API clk: imx: clk-fixup-div: Switch to clk_hw based API clk: imx: clk-gate-exclusive: Switch to clk_hw based API clk: imx: clk-pfd: Switch to clk_hw based API clk: imx: clk-pllv3: Switch to clk_hw based API clk: imx: clk-gate2: Switch to clk_hw based API clk: imx: clk-cpu: Switch to clk_hw based API ... * clk-allwinner: (29 commits) clk: Simplify debugfs printing and add a newline clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE clk: sunxi-ng: gate: Add macros for referencing local clock parents clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_* clk: sunxi-ng: switch to of_clk_hw_register() for registering clks clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent ...
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Stephen Boyd authored
Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next * clk-qcom-gdsc-warn: clk: qcom: gdsc: WARN when failing to toggle * clk-ingenic: MIPS: Remove dead code clk: ingenic: Remove unused functions MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode clk: ingenic: Handle setting the Low-Power Mode bit clk: ingenic: Add missing header in cgu.h clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly clk: ingenic/jz4725b: Fix incorrect dividers for main clocks clk: ingenic/jz4770: Fix incorrect dividers for main clocks clk: ingenic/jz4740: Fix incorrect dividers for main clocks clk: ingenic: Add support for divider tables * clk-qcom-qcs404-reset: clk: gcc-qcs404: Add PCIe resets * clk-xgene-limit: clk: xgene: Don't build COMMON_CLK_XGENE by default * clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
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Stephen Boyd authored
Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next - Add support to get duty cycle of generic pwm clks * clk-pwm-duty: clk: pwm: implement the .get_duty_cycle callback * clk-bcm: clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB clk: bcm: Make BCM2835 clock drivers selectable * clk-mtk: clk: mediatek: Remove MT8183 unused clock clk: mediatek: add audsys clock driver for MT8516 dt-bindings: mediatek: audsys: add support for MT8516 * clk-qcom-msm8998-gpu: dt-bindings: clock: Document gpucc for msm8998 * clk-renesas: clk: renesas: cpg-mssr: Use [] to denote a flexible array member clk: renesas: cpg-mssr: Combine driver-private and clock array allocation clk: renesas: mstp: Combine group-private and clock array allocation clk: renesas: div6: Combine clock-private and parent array allocation clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv clk: renesas: r8a774a1: Add TMU clock clk: renesas: r8a77995: Add CMM clocks clk: renesas: r8a77990: Add CMM clocks clk: renesas: r8a77965: Add CMM clocks clk: renesas: r8a7795: Add CMM clocks clk: renesas: r9a06g032: Add clock domain support dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains clk: renesas: mstp: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Use genpd of_node instead of local copy clk: renesas: r8a7796: Add CMM clocks clk: renesas: r8a779{5|6|65}: Add TPU clock -
Stephen Rothwell authored
Without this we were getting errors like: In file included from drivers/clk/clkdev.c:22:0: drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here Fixes: 59fcdce4 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h") fixes: 73e0e496 ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF") Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 27 Jun, 2019 8 commits
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Chunyan Zhang authored
sprd_clk_regmap_init() doesn't always return success, adding check for its return value should make the code more strong. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Reviewed-by:
Baolin Wang <baolin.wang@linaro.org> [sboyd@kernel.org: Add a missing int ret] Signed-off-by:
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Claudiu Beznea authored
Use at91 specific functions to free all resources in case of error. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Claudiu Beznea authored
Improve error path for sama5d4 sck registration. Signed-off-by:
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Claudiu Beznea authored
Remove unnecessary line. Signed-off-by:
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Claudiu Beznea authored
Improve error path for sam9x5 slow clock registration. Signed-off-by:
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Claudiu Beznea authored
Add support to free slow clock oscillator resources. Signed-off-by:
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Claudiu Beznea authored
Add support to free slow rc oscillator resources. Signed-off-by:
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Claudiu Beznea authored
Add support to free slow oscillator resources. Signed-off-by:
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- 26 Jun, 2019 6 commits
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Claudiu Beznea authored
Add support for SAM9X60's slow clock. Signed-off-by:
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Claudiu Beznea authored
Add bindings for SAM9X60's slow clock controller. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Claudiu Beznea authored
Different IPs uses different bit offsets in registers for the same functionality, thus adapt the driver to support this. Signed-off-by:
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Claudiu Beznea authored
The slow clock of SAMA5D4 has no bypass support thus remove it. Signed-off-by:
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Chunyan Zhang authored
The function devm_regmap_init_mmio() wouldn't return NULL pointer for now, so only need to ensure the return value is not an error code. Signed-off-by:
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Chunyan Zhang authored
devm_ioremap_resources() automatically requests resources and devm_ wrappers do better error handling and unmapping of the I/O region when needed, that would make drivers more clean and simple. Signed-off-by:
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- 25 Jun, 2019 19 commits
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Thierry Reding authored
It turns out that this PLL is not used on Tegra210, so there's no need to enable it via the init table. Remove the init table entry for this PLL to avoid it getting enabled at boot time. If the bootloader enabled it and forgot to turn it off, the common clock framework will now know to disable it because it is unused. Signed-off-by:
Thierry Reding <treding@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
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Thierry Reding authored
A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a configuration that makes sense, so warn about it. Signed-off-by:
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Thierry Reding authored
There is no need to warn if the reference PLL is enabled with the correct defaults. Only warn if the boot values don't match the defaults. Signed-off-by:
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JC Kuo authored
Full-speed and low-speed USB devices do not work with Tegra210 platforms because of incorrect PLLU/PLLU_OUT1 clock settings. When full-speed device is connected: [ 14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb [ 14.196295] usb 1-3: device descriptor read/64, error -71 [ 14.436311] usb 1-3: device descriptor read/64, error -71 [ 14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb [ 14.812335] usb 1-3: device descriptor read/64, error -71 [ 15.052316] usb 1-3: device descriptor read/64, error -71 [ 15.164799] usb usb1-port3: attempt power cycle When low-speed device is connected: [ 37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad? [ 38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad? [ 38.564977] usb usb1-port3: attempt power cycle This commit fixes the issue by: 1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock because PLLU_OUT1 is parent of XUSB_FS_SRC. 2. changing PLLU post-divider to /2 (DIVP=1) according to Technical Reference Manual. Fixes: e745f992 ("clk: tegra: Rework pll_u") Signed-off-by:JC Kuo <jckuo@nvidia.com> Acked-By:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
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Nicolas Saenz Julienne authored
As 'clk-raspberrypi' depends on RPi's firmware interface, which might be configured as a module, the cpu clock might not be available for the cpufreq driver during it's init process. So we register the 'raspberrypi-cpufreq' platform device after the probe sequence succeeds. Signed-off-by:
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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Nicolas Saenz Julienne authored
Since clk-raspberrypi is tied to the VC4 firmware instead of particular hardware it's registration should be performed by the firmware driver. Signed-off-by:
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Nicolas Saenz Julienne authored
Raspberry Pi's firmware offers an interface though which update it's clock's frequencies. This is specially useful in order to change the CPU clock (pllb_arm) which is 'owned' by the firmware and we're unable to scale using the register interface provided by clk-bcm2835. Signed-off-by:
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Nicolas Saenz Julienne authored
Raspberry Pi's firmware controls this pll, we should use the firmware interface to access it. Signed-off-by:
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Vabhav Sharma authored
Add clockgen support and configuration for NXP SoC lx2160a with compatible property as "fsl,lx2160a-clockgen". Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Signed-off-by:
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by:
Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by:
Scott Wood <oss@buserror.net> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Wolfram Sang authored
We have a dedicated pointer for that, so use it. Much easier to read and less computation involved. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Nathan Huckleberry authored
Clang produces the following warning drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = { ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^ drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^ drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = { It looks like these were never used. Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Cc: clang-built-linux@googlegroups.com Link: https://github.com/ClangBuiltLinux/linux/issues/518Suggested-by:Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
Nathan Huckleberry <nhuck@google.com> Reviewed-by:
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Paul Cercueil authored
Remove the unused <asm/mach-jz4740/clock.h> include. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Acked-by:
Paul Burton <paul.burton@mips.com> Signed-off-by:
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Paul Cercueil authored
These functions are not called anywhere anymore, they can safely be removed. Signed-off-by:
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Paul Cercueil authored
Instead of forcing the jz4740 clocks to suspend here, we let the CGU driver handle it. We also let the CGU driver set the "sleep mode" bit. This has the added benefit that now it is possible to build a kernel on SoCs newer than the JZ4740 with CONFIG_PM. Signed-off-by:
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Paul Cercueil authored
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by:
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Paul Cercueil authored
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw' structures (no pointers), so the <linux/clk-provider.h> header should be included. Signed-off-by:
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Leonard Crestez authored
This allows to easily determine the parent in shell scripts without parsing more complex files. Add the clk_parent file for all clks which can have a parent, not just muxes. This way it can be used to determine the clk tree structure without parsing more complex files. Signed-off-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Geert Uytterhoeven authored
A boolean expression already evaluates to true or false, so there is no need to check the result and return true or false explicitly. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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