- 02 Aug, 2019 4 commits
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Monk Liu authored
previously the ucode loading of PSP was repreated, one executed in phase_1 init/re-init/resume and the other in fw_loading routine Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset prior to the FW loading and any block's hw_init/resume v2: still do the smu fw loading since it is needed by bare-metal v3: drop the change in reinit_early_sriov, just clear all block's status.hw in the head place and set the status.hw after hw_init done is enough Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
for SRIOV the SOS fw of PSP is loaded in hypervisor thus guest won't tell the version of it, and judging feature by reading the sos fw version in guest side is completely wrong Signed-off-by:
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Monk Liu authored
we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by:
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Kevin Wang authored
before this change, the pp_feature sysfs show feature enable state by logic feature id, it is not easy to read. this change will sort pp_features show index by asic feature id. before: features high: 0x00000623 low: 0xb3cdaffb 00. DPM_PREFETCHER ( 0) : enabeld 01. DPM_GFXCLK ( 1) : enabeld 02. DPM_UCLK ( 3) : enabeld 03. DPM_SOCCLK ( 4) : enabeld 04. DPM_MP0CLK ( 5) : enabeld 05. DPM_LINK ( 6) : enabeld 06. DPM_DCEFCLK ( 7) : enabeld 07. DS_GFXCLK (10) : enabeld 08. DS_SOCCLK (11) : enabeld 09. DS_LCLK (12) : disabled 10. PPT (23) : enabeld 11. TDC (24) : enabeld 12. THERMAL (33) : enabeld 13. RM (35) : disabled ...... after: features high: 0x00000623 low: 0xb3cdaffb 00. DPM_PREFETCHER ( 0) : enabeld 01. DPM_GFXCLK ( 1) : enabeld 02. DPM_GFX_PACE ( 2) : disabled 03. DPM_UCLK ( 3) : enabeld 04. DPM_SOCCLK ( 4) : enabeld 05. DPM_MP0CLK ( 5) : enabeld 06. DPM_LINK ( 6) : enabeld 07. DPM_DCEFCLK ( 7) : enabeld 08. MEM_VDDCI_SCALING ( 8) : enabeld 09. MEM_MVDD_SCALING ( 9) : enabeld 10. DS_GFXCLK (10) : enabeld 11. DS_SOCCLK (11) : enabeld 12. DS_LCLK (12) : disabled 13. DS_DCEFCLK (13) : enabeld ...... Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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- 31 Jul, 2019 36 commits
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Alex Deucher authored
Same as navi10. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Dennis Li authored
some subblocks of gfx fail in inject test, disable them Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Dennis Li authored
check gfx error count in both ras querry function and ras interrupt handler. gfx ras is still disabled by default due to known stability issue found in gpu reset. Signed-off-by:
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Dennis Li authored
Add functions for RAS error inject and query error counter Signed-off-by:
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Dennis Li authored
Signed-off-by:
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Dennis Li authored
Signed-off-by:
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Dennis Li authored
Add EDC registers to support VEGA20 RAS Signed-off-by:
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Tao Zhou authored
error injection address is not in gpu address space Signed-off-by:
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Tao Zhou authored
only ue and ce errors are supported Signed-off-by:
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Tao Zhou authored
add err_data parameter in interrupt cb for ras clients Signed-off-by:
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Tao Zhou authored
add error data as parameter for ras interrupt cb and process it Signed-off-by:
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Tao Zhou authored
query umc ras error address, translate it to gpu 4k page view and save it. Signed-off-by:
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Tao Zhou authored
add related registers, callback function and channel index table Signed-off-by:
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Tao Zhou authored
more than one error address may be recorded in one query Signed-off-by:
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Tao Zhou authored
remove the check of ErrorCodeExt v2: refine the if condition for ue counting Signed-off-by:
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Tao Zhou authored
create new amdgpu_umc structure to for more umc settings in future and switch to the new structure Signed-off-by:
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Tao Zhou authored
replace some 32bit macros with 64bit operations to simplify code Signed-off-by:
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Tao Zhou authored
add 64 bits register access functions v2: implement 64 bit functions in low level Signed-off-by:
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Tao Zhou authored
v1: increase ras ce/ue error count v2: log the number of correctable and uncorrectable errors Signed-off-by:
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Hawking Zhang authored
check umc error count in both ras querry function and ras interrupt handler Signed-off-by:
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Hawking Zhang authored
init umc callback function for vega20 in sw early init phase Signed-off-by:
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Hawking Zhang authored
Implement umc query_ras_error_count function to support querry both correctable and uncorrectable error Signed-off-by:
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Hawking Zhang authored
the change introduces IP headers for unified memory controller (umc) Signed-off-by:
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Hawking Zhang authored
remote smu (rsmu) is a sub-block used as ip register interface, error handling, reset generation.etc Signed-off-by:
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Hawking Zhang authored
This is common structure as UMC callback function Signed-off-by:
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Hawking Zhang authored
the driver needs to program RSMU and UMC registers to support vega20 RAS feature Signed-off-by:
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Hawking Zhang authored
These are common structures that can be included by IP specific source files Signed-off-by:
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Alex Deucher authored
Unused. Acked-by:
Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
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Alex Deucher authored
And fix the fallout. Acked-by:
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Alex Deucher authored
And fix the fallout. Acked-by:
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Alex Deucher authored
And fix up the fallout. Acked-by:
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Alex Deucher authored
And fix the fallout. Acked-by:
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Alex Deucher authored
And fix the fallout. Acked-by:
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Alex Deucher authored
Unused. Acked-by:
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Alex Deucher authored
Unused. Acked-by:
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Evan Quan authored
Per current logics, the features to enable are determined together by driver and pptable. This is not efficient in co-debug with firmware team. Signed-off-by:
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