1. 29 Jun, 2017 36 commits
  2. 28 Jun, 2017 4 commits
    • Huacai Chen's avatar
      MIPS: Loongson: Add Loongson-3A R3 basic support · 0a00024d
      Huacai Chen authored
      Loongson-3A R3 is very similar to Loongson-3A R2.
      
      All Loongson-3 CPU family:
      
      Code-name       Brand-name       PRId
      Loongson-3A R1  Loongson-3A1000  0x6305
      Loongson-3A R2  Loongson-3A2000  0x6308
      Loongson-3A R3  Loongson-3A3000  0x6309
      Loongson-3B R1  Loongson-3B1000  0x6306
      Loongson-3B R2  Loongson-3B1500  0x6307
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: John Crispin <john@phrozen.org>
      Cc: Steven J . Hill <Steven.Hill@cavium.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16585/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      0a00024d
    • Paul Burton's avatar
      MIPS: SEAD-3: Fix GIC interrupt specifiers · d3f61634
      Paul Burton authored
      The various interrupt specifiers in the device tree are not in a valid
      format for the MIPS GIC interrupt controller binding. Where each
      interrupt should provide 3 values - GIC_LOCAL or GIC_SHARED, the
      pin number & the type of interrupt - the device tree was only providing
      the pin number. This causes interrupts for those devices to not be used
      when a GIC is present. SEAD-3 systems without a GIC are unaffected since
      the DT fixup code generates interrupt specifiers that are valid for the
      CPU interrupt controller.
      
      Fix this by adding the GIC_SHARED & IRQ_TYPE_LEVEL_HIGH values to each
      interrupt specifier.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Fixes: c11e3b48 ("MIPS: SEAD3: Probe UARTs using DT")
      Fixes: a34e9388 ("MIPS: SEAD3: Probe ethernet controller using DT")
      Fixes: 7afd2a5a ("MIPS: SEAD3: Probe EHCI controller using DT")
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org  # v4.9+
      Patchwork: https://patchwork.linux-mips.org/patch/16189/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      d3f61634
    • Paul Burton's avatar
      MIPS: SEAD-3: Set interrupt-parent per-device, not at root node · fbdc674b
      Paul Burton authored
      The SEAD-3 board may be configured with or without a MIPS Global
      Interrupt Controller (GIC). Because of this we have a device tree with a
      default case of a GIC present, and code to fixup the device tree based
      upon a configuration register that indicates the presence of the GIC.
      
      In order to keep this DT fixup code simple, the interrupt-parent
      property was specified at the root node of the SEAD-3 DT, allowing the
      fixup code to simply change this property to the phandle of the CPU
      interrupt controller if a GIC is not present & affect all
      interrupt-using devices at once. This however causes a problem if we do
      have a GIC & the device tree is used as-is, because the interrupt-parent
      property of the root node applies to the CPU interrupt controller node.
      This causes a cycle when of_irq_init() attempts to probe interrupt
      controllers in order and boots fail due to a lack of configured
      interrupts, with this message printed on the kernel console:
      
      [    0.000000] OF: of_irq_init: children remain, but no parents
      
      Fix this by removing the interrupt-parent property from the DT root node
      & instead setting it for each device which uses interrupts, ensuring
      that the CPU interrupt controller node has no interrupt-parent &
      allowing of_irq_init() to identify it as the root interrupt controller.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Reported-by: default avatarKeng Koh <keng.koh@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16187/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      fbdc674b
    • Paul Burton's avatar
      MIPS: generic: Add a MAINTAINERS entry · 032a469b
      Paul Burton authored
      Add an entry to MAINTAINERS for the generic platform code, such that
      relevant people, starting with myself, can be CC'd on patches.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16186/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      032a469b