1. 17 Jan, 2007 1 commit
  2. 03 Jan, 2007 1 commit
  3. 29 Dec, 2006 1 commit
  4. 23 Dec, 2006 2 commits
    • Eric Anholt's avatar
      [AGPGART] fix detection of aperture size versus GTT size on G965 · c41e0deb
      Eric Anholt authored
      On the G965, the GTT size may be larger than is required to cover the
      aperture.  (In fact, on all hardware we've seen, the GTT is 512KB to the
      aperture's 256MB).  A previous commit forced the aperture size to 512MB on
      G965 to match GTT, which would likely result in hangs at best if users
      tried to rely on agpgart's aperture size information.  Instead, we use the
      resource length for the aperture size and the system's reported GTT size
      when available for the GTT size.
      
      Because the MSAC registers which had been read for aperture size detection
      on i9xx chips just cause a change in the resource size, we can use generic
      code for aperture detection on all i9xx.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      c41e0deb
    • Thomas Hellstrom's avatar
      [AGPGART] Remove unnecessary flushes when inserting and removing pages. · 5aa80c72
      Thomas Hellstrom authored
      This patch is to speed up flipping of pages in and out of the AGP aperture as
      needed by the new drm memory manager.
      
      A number of global cache flushes are removed as well as some PCI posting flushes.
      The following guidelines have been used:
      
      1) Memory that is only mapped uncached and that has been subject to a global
      cache flush after the mapping was changed to uncached does not need any more
      cache flushes. Neither before binding to the aperture nor after unbinding.
      
      2) Only do one PCI posting flush after a sequence of writes modifying page
      entries in the GATT.
      Signed-off-by: default avatarThomas Hellstrom <thomas@tungstengraphics.com>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      5aa80c72
  5. 19 Dec, 2006 1 commit
  6. 18 Dec, 2006 5 commits
  7. 17 Dec, 2006 10 commits
  8. 16 Dec, 2006 16 commits
  9. 15 Dec, 2006 3 commits
    • Linus Torvalds's avatar
      Fix "delayed_work_pending()" macro expansion · 0221872a
      Linus Torvalds authored
      Nobody uses it, but it was still wrong.  Using the macro argument name
      'work' meant that when we used 'work' as a member name, that would also
      get replaced by the macro argument.
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      0221872a
    • Roland Dreier's avatar
      IB/srp: Fix FMR mapping for 32-bit kernels and addresses above 4G · bf628dc2
      Roland Dreier authored
      struct srp_device.fmr_page_mask was unsigned long, which means that
      the top part of addresses above 4G was being chopped off on 32-bit
      architectures.  Of course nothing good happens when data from SRP
      targets is DMAed to the wrong place.
      
      Fix this by changing fmr_page_mask to u64, to match the addresses
      actually used by IB devices.
      
      Thanks to Brian Cain <Brian.Cain@ge.com> and David McMillen
      <davem@systemfabricworks.com> for help diagnosing the bug and testing
      the fix.
      Signed-off-by: default avatarRoland Dreier <rolandd@cisco.com>
      bf628dc2
    • Roland Dreier's avatar
      IB: Fix ib_dma_alloc_coherent() wrapper · c59a3da1
      Roland Dreier authored
      The ib_dma_alloc_coherent() wrapper uses a u64* for the dma_handle
      parameter, unlike dma_alloc_coherent, which uses dma_addr_t*.  This
      means that we need a temporary variable to handle the case when
      ib_dma_alloc_coherent() just falls through directly to
      dma_alloc_coherent() on architectures where sizeof u64 != sizeof
      dma_addr_t.
      Signed-off-by: default avatarRoland Dreier <rolandd@cisco.com>
      c59a3da1