- 17 Jun, 2009 40 commits
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David Daney authored
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove it to mach-cavium-octeon/cpu-feature-overrides.h Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Add new kconfig variables SYS_SUPPORTS_HUGETLBFS and CPU_SUPPORTS_HUGEPAGES. They are enabled for systems that are known to support huge pages. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
As part of adding hugetlbfs support for MIPS, I am adding a new kconfig variable 'SYS_SUPPORTS_HUGETLBFS'. Since some mips cpu varients don't yet support it, we can enable selection of HUGETLBFS on a system by system basis from the arch/mips/Kconfig. Signed-off-by: David Daney <ddaney@caviumnetworks.com> CC: William Irwin <wli@holomorphy.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The TLB handlers need to check for huge pages and give them special handling. Huge pages consist of two contiguous sub-pages of physical memory. * Loading entrylo0 and entrylo1 need to be handled specially. * The page mask must be set for huge pages and then restored after writing the TLB entries. * The PTE for huge pages resides in the PMD, we halt traversal of the tables there. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The l parameter to iPTE_LW() is unused. Remove it and from some of its callers as well. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The octeon-ethernet driver supports the sgmii, rgmii, spi, and xaui ports present on the Cavium OCTEON family of SOCs. These SOCs are multi-core mips64 processors with existing support over in arch/mips. The driver files can be categorized into three basic groups: 1) Register definitions, these are named cvmx-*-defs.h 2) Main driver code, these have names that don't start cvmx-. 3) Interface specific functions and other utility code, names starting with cvmx- Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The octeon-ethernet driver needs to check for additional chip specific features, we add them to the octeon_has_feature() framework. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The bootloader now uses additional board type constants. The octeon-ethernet driver needs some of the new values. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The various Octeon ethernet drivers use these new functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Manuel Lauss authored
Replace a few open-coded GPIO register accesses with gpio calls. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Manuel Lauss authored
Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Manuel Lauss authored
Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Manuel Lauss authored
The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. See arch/mips/include/asm/mach-au1x00/gpio.h for more info. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Manuel Lauss authored
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Matthieu Castet authored
gpio_direction_output should also set an output value according to the API. Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
o Rewrite to use <asm-generic/ioctl.h>. Cuts down the file from 40 to 16 lines. o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT. They were added for 2.1.14 but I was not able to find any user - not even historical ones. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
Add platform support for RNG of TX4939 SoC. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
This patch adds support for the integrated RNG of the TX4939 SoC. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Matt Mackall <mpm@selenic.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
Add a sysdev to access SRAM in TXx9 SoCs via sysfs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Imre Kaloz authored
CFE is the only supported and used bootloader on the SiByte boards, the standalone kernel support has been never used outside Broadcom. Remove it and make the kernel use CFE by default. Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Imre Kaloz authored
This patch removes the SiByte simulation Kconfig option, which only modified a printk. Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Florian Fainelli authored
This patch makes sure that we are not going to clear or change the interrupt status of a GPIO interrupt superior to 13 as this is the maximum number of GPIO interrupt source (p.232 of the RC32434 reference manual). Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Florian Fainelli authored
Remove commented out definitions. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch. This label in the switch statement is dead code, so we remove it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Try to fold the 64-bit TLB refill handler opportunistically at the beginning of the vmalloc path so as to avoid splitting execution flow in half and wasting cycles for a branch required at that point then. Resort to doing the split if either of the newly created parts would not fit into its designated slot. Original-patch-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The logic used to split the r4000 refill handler is liberally sprinkled with magic numbers. We attempt to explain what they are and normalize them against a new symbolic value (MIPS64_REFILL_INSNS). CC: David VomLehn <dvomlehn@cisco.com> Reviewed-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
Add platform support for ACLC of TXx9 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
This patch adds support for PCI and PCIe to the base Cavium OCTEON processor support. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
Here we add the register definitions for the processor blocks used by the following PCI support patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
Add platform support for DMAC of TXx9 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
This patch adds support for the integrated DMAC of the TXx9 family. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Atsushi Nemoto authored
Use container structure for clocksource, clock_event_device and hold a pointer to txx9_tmr_reg in it. This saves a few instructions in clocksource and clock_event handlers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Kevin Cernekee authored
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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