- 10 May, 2019 14 commits
-
-
Helge Deller authored
Signed-off-by:Helge Deller <deller@gmx.de>
-
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Helge Deller authored
This patch modifies the initial page mapping functions in the following way: During bootup the init, text and data pages will be mapped RWX and if supported, with huge pages. At final stage of the bootup, the kernel calls free_initmem() and then all pages will be remapped either R-X (for text and read-only data) or RW- (for data). The __init pages will be dropped. This reflects the behaviour of the x86 platform. Signed-off-by: -
Helge Deller authored
When running an SMP kernel on a single-CPU machine, we can speed up the CAS code by replacing the LDCW sync barrier with NOP. Signed-off-by:
-
- 05 May, 2019 3 commits
-
-
Helge Deller authored
Signed-off-by: -
Helge Deller authored
The LEVEL define clashed with the DRBD code. Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
-
Helge Deller authored
LEVEL is a very common word, and now after many years it suddenly clashed with another LEVEL define in the DRBD code. Rename it to PA_ASM_LEVEL instead. Reported-by:
-
- 03 May, 2019 23 commits
-
-
John David Anglin authored
This patch updates the parisc huge TLB page support to use per-pagetable spinlocks. This patch requires Mikulas' per-pagetable spinlock patch and the revised TLB serialization patch from Helge and myself. With Mikulas' patch, we need to use the per-pagetable spinlock for page table updates. The TLB lock is only used to serialize TLB flushes on machines with the Merced bus. Signed-off-by:
John David Anglin <dave.anglin@bell.net> Signed-off-by:
-
Mikulas Patocka authored
PA-RISC uses a global spinlock to protect pagetable updates in the TLB fault handlers. When multiple cores are taking TLB faults simultaneously, the cache line containing the spinlock becomes a bottleneck. This patch embeds the spinlock in the top level page directory, so that every process has its own lock. It improves performance by 30% when doing parallel compilations. At least on the N class systems, only one PxTLB inter processor broadcast can be active at any one time on the Merced bus. If a Merced bus is found, this patch serializes the TLB flushes with the pa_tlb_flush_lock spinlock. v1: Initial patch by Mikulas v2: Added Merced detection by Helge v3: Revised TLB serialization by Dave & Helge Signed-off-by:
Mikulas Patocka <mpatocka@redhat.com> Signed-off-by:
-
Helge Deller authored
When making the text sections writeable with set_kernel_text_rw(1), include all text sections including those in the __init section. Otherwise functions marked with __meminit will stay read-only. Signed-off-by: -
Helge Deller authored
Add compiler memory barriers to ensure the compiler doesn't reorder memory operations around these instructions. Cc: stable@vger.kernel.org # v4.20+ Fixes: 3847dab7 ("parisc: Add alternative coding infrastructure") Signed-off-by:
-
John David Anglin authored
The pdtlb and pitlb instructions are strongly ordered. The asms invoking these instructions should be compiler memory barriers to ensure the compiler doesn't reorder memory operations around these instructions. Signed-off-by:
-
John David Anglin authored
There are only a couple of instructions that can function as a memory barrier on parisc. Currently, we use the sync instruction as a memory barrier when releasing a spinlock. However, the ldcw instruction is a better barrier when we have a handy memory location since it operates in the cache on coherent machines. This patch updates the spinlock release code to use ldcw. I also changed the "stw,ma" instructions to "stw" instructions as it is not an adequate barrier. Signed-off-by:
-
John David Anglin authored
TLB operations only need to be serialized on machines with the Merced (Stretch) bus. The only machines in this category are L and N class, and they require a 64-bit PA 2.0 kernel. On these machines, we use local TLB purges in the tmpalias routines. We don't need to serialize TLB purges on all other machines. Thus, the lock/unlock code can be removed when CONFIG_PA20 is not defined. Further, when CONFIG_PA20 is not defined, alternative patching converts the TLB purges to local purges when PA 2.0 hardware has been detected. Signed-off-by:
Sven Schnelle <svens@stackframe.org> Signed-off-by:
-
Helge Deller authored
The commit 1c30844d ("mm: reclaim small amounts of memory when an external fragmentation event occurs") breaks memory management on a parisc c8000 workstation with this memory layout: 0) Start 0x0000000000000000 End 0x000000003fffffff Size 1024 MB 1) Start 0x0000000100000000 End 0x00000001bfdfffff Size 3070 MB 2) Start 0x0000004040000000 End 0x00000040ffffffff Size 3072 MB With the patch 1c30844d, the kernel will incorrectly reclaim the first zone when it fills up, ignoring the fact that there are two completely free zones. Basiscally, it limits cache size to 1GiB. The parisc kernel is currently using the DISCONTIGMEM implementation, but isn't NUMA. Avoid this issue or strange work-arounds by switching to the more commonly used SPARSEMEM implementation. Reported-by:
-
Sven Schnelle authored
The idle task might have been allocated above 4GB. With the current code we cannot access that memory because the CPU is still running in narrow mode. This was found on a J5000 machine and the patch is required to enable SPARSEMEM on that machine. Signed-off-by:
-
Sven Schnelle authored
Update lists to reflect that we have now KGDB and kretprobes support. Signed-off-by:
-
Helge Deller authored
Signed-off-by: -
Sven Schnelle authored
It's not used by patch_map()/patch_unmap(), so lets remove it. Signed-off-by:
-
Sven Schnelle authored
Now that kprobes and kretprobes are implemented, update the list in Documentation to reflect that. Signed-off-by:
-
Sven Schnelle authored
Implement kretprobes on parisc, parts stolen from powerpc. Signed-off-by:
-
Sven Schnelle authored
We're providing our own version now. Signed-off-by:
-
Sven Schnelle authored
Implement kprobes support for PA-RISC. Signed-off-by:
-
Sven Schnelle authored
implement regs_get_register(), regs_get_kernel_stack_nth() and regs_within_kernel_stack() Signed-off-by:
-
Helge Deller authored
Even a 32-bit kernel requires at least 27 MB to decompress itself, so halt the system with a message if the system has less memory than 32 MB. Signed-off-by: -
Helge Deller authored
No need to spend CPU cycles when we run on QEMU. Signed-off-by: -
Helge Deller authored
Do not loose cycles when we run on QEMU, and fix one trivial typo. Signed-off-by: -
Helge Deller authored
Signed-off-by: -
Sven Schnelle authored
This patch add KGDB support to PA-RISC. It also implements single-stepping utilizing the recovery counter. Signed-off-by:
-
Sven Schnelle authored
Instead of re-mapping the whole kernel text with RWX rights add a patch_text() which can be used to replace instructions in the kernel .text section. Based on the ARM implementation. Signed-off-by:
-
