- 25 Apr, 2013 12 commits
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Daniel Vetter authored
g4x dplls and ilk+ pch plls have a separate field for the reduced p1 setting, so this restriction does not apply. Only older platforms have the restriction that the p1 divisors must match. This unnecessary restriction has been introduced in commit cec2f356 Author: Sean Paul <seanpaul@chromium.org> Date: Tue Jan 10 15:09:36 2012 -0800 drm/i915: Only look for matching clocks for LVDS downcloc Note that with lvds the p2 divisors _always_ match for LVDS, and we don't support auto-downclocking anywhere else. On eDP downclocking works with separate data m/n settings, using the same link clock. Cc: Sean Paul <seanpaul@chromium.org> Reviewed-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Up to now we've relied on the bios to get this right for us. Let's try out whether our code has improved a bit, since we should dither always when the output bpp doesn't match the plane bpp. - gen5+ should be fine, since we only use the bios hint as an upgrade. - gen4 changes, since here dithering is still controlled in the lvds register. - gen2/3 has implicit dithering depeding upon whether you use 2 or 3 lvds pairs (which makes sense, since it only supports 8bpc pipe outpu configurations). - hsw doesn't support lvds. v2: Remove redudant dither setting. v3: Completly drop reliance on dev_priv->lvds_dither. v4: Enable dithering on gen2/3 only when we have a 18bpp panel, since up-dithering to a 24bpp panel is not supported by the hw. Spotted by Ville. v5: Also only enable lvds port dithering on gen4 for 18bpp modes. In practice this only excludes dithering a 10bpc plane down for a 24bpp lvds panel. Not something we truly care about. Again noticed by Ville. v6: Actually git add. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Daniel Vetter authored
With the exception of hsw, which has dedicated DP clocks which run at the fixed frequency already, and vlv, which doesn't have optmized pre-defined dp clock parameters (yet). v2: Ville asked me to elaborate a bit more on the longer-term goals wrt dpll settings computation: So ultimately my idea is that in the compute config stage first the crtc code puts the default platform pll limits into the pipe_config. Then encoders can either overwrite that limit structure with their own special stuff (mostly for lvds madness). Or they can pick some or all of the parameters (e.g. just the p2 switchover on hdmi, or all the clock parameters for dp/sdvo tv). Once that's done then the generic crtc code can fill out any missing bits (using the find_best_pll code) and then try to assign which pll to use (if it's a platform with shared plls). In the end the modeset could should simply write the computed stuff into registers and never be able to fail. Of course there's still a lot of data to be moved into pipe_config to make this all happen, hence some of the temporary ugliness. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1) Reviewed-by:
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Daniel Vetter authored
This was somehow lost in the pipe_config->dpll introduction in commit f47709a9 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Mar 28 10:42:02 2013 +0100 drm/i915: create pipe_config->dpll for clock state While at it, extract a few small helpers for common computations. v2: Use the newly added helpers more thanks to Ville's trick to typedef the legacy intel_clock_t as the new-world struct dpll. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniel Vetter authored
We need the dpll/fp/fp2 values only when we need a pch pll. So move them together with the code to acquire such a pll. Reviewed-by:
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Damien Lespiau authored
Between ivb, hsw and vlv, only Ivybridge has sprites with scaling capabilities. Also make max_downscale coherent with that. v2: Rebase on top of the recent ivb/vlv/hsw sprite scaling fixes. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1) Reviewed-by:
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Jani Nikula authored
v2: Make TRANSCODER_EDP handling more explicit. (Imre) Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
With the previous work asle and gse interrupt handlers should now be functionally the same. Drop the duplicated code. v2: Drop intel_opregion_gse_intr() also in the !CONFIG_ACPI path. (Damien) Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Jani Nikula authored
In theory, the BIOS should not even request these from us now that we aren't claiming we support these, but when it does anyway, don't pretend it succeeded. It should be the right thing to do, but might confuse the BIOS. Signed-off-by:
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Jani Nikula authored
In theory, this should prevent the BIOS from requesting them from us, and this should be the right thing. In practice, this is not always the case, and might surprise the BIOS. Signed-off-by:
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Jani Nikula authored
Backlight data and registers are fiddled through LVDS/eDP modeset enable/disable hooks, backlight sysfs files, asle interrupts, and register save/restore. Protect the backlight related registers and driver private fields using a spinlock. The locking in register save/restore covers a little more than is strictly necessary, including non-modeset case, for simplicity. v2: Cover register access, save/restore, i915_read_blc_pwm_ctl() and code paths leading there. Signed-off-by: -
Jani Nikula authored
In preparation of adding locking to backlight, make max backlight value (the modulation frequency the PWM duty cycle value must not exceed) internal to intel_panel.c. Have intel_panel_set_backlight() accept a caller defined range for level, and scale input to max backlight value internally. Clean up intel_panel_get_max_backlight() and usage internally. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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- 24 Apr, 2013 6 commits
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Daniel Vetter authored
The LPT PCH only supports 8bpc, so we need to force the pipe bpp to the right value. Reviewed-by:
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Daniel Vetter authored
Prevents black screens when using 30bpp framebuffers on my HDMI screens here. The DP input on the same screen though reports a 1.4 EDID with the correct 8bpc limit set. v2: Actually check for the right thing! Reviewed-by:
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Daniel Vetter authored
Our rps code relies on the interrupts being off to prevent re-arming of the work items at inopportune moments. Also drop the redundant cancel_work for the main rps work, disable_gt_powersave already takes care of that. Finally add a WARN_ON to ensure we obey that piece of ordering constraint. Long term I want to lock down the setup/teardown code in a similar way to how we painstakingly check modeset sequence constraints already. v2: Disable polling after hpd handling is shut down - since Egbert's hpd irq storm handling the hotplug work can re-arm the polling handler. Spotted by Jani Nikula. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Jesse Barnes authored
We don't want to write reserved regs here, and may want to do other bits in the future, so split it out. Reported-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
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Jesse Barnes authored
Ville noticed this while doing another review; we may as well cancel this work just to make sure we don't try anything fancy after disabling the RPS interfaces. Reported-by:
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Jesse Barnes authored
On VLV, the Punit doesn't automatically drop the GPU to it's minimum voltage level when entering RC6, so we arm a timer to do it for us from the RPS interrupt handler. It'll generally only fire when we go idle (or if for some reason there's a long delay between RPS interrupts), but won't be re-armed again until the next RPS event, so shouldn't affect power consumption after we go idle and it triggers. v2: use delayed work instead of timer + work queue combo (Ville) v3: fix up delayed work cancel (must be outside lock) (Daniel) fix up delayed work handling func for delayed work (Jesse) v4: cancel delayed work before RPS shutdown (Jani) pass delay not absolute time to mod_delayed_work (Jani) Signed-off-by:
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- 23 Apr, 2013 9 commits
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Damien Lespiau authored
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Damien Lespiau authored
Let's introduce one more of those orthogonal feature macros. This should hopefully make the code more readable and make things easier for new platform enabling. This time, HAS_FPGA_DBG_UNCLAIMED() is true for platforms that have bit 31 of FPGA_DBG able to signal unclaimed writes. Signed-off-by:
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Damien Lespiau authored
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Damien Lespiau authored
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Damien Lespiau authored
This way, when adding a device flag we don't have to manually maintain that list. v2: undefine the helper macros (Jani Nikula, Daniel Vetter) Signed-off-by:
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Damien Lespiau authored
DEV_INFO_FOR_FLAG() now takes 2 parameters: • A function to apply to the flag • A separator This will allow us to use the macro twice in the DRM_DEBUG_DRIVER() call of i915_dump_device_info(). v2: Fix a typo in the subject (Jani Nikula) v3: Undef the helper macros (Jani Nikula, Daniel vetter) Reviewed-by:
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Egbert Eich authored
Instead of calling into the DRM helper layer to poll all connectors for changes in connected displays probe only those connectors which have received a hotplug event. v2: Resolved conflicts with changes in previous commits. Renamed function and and added a WARN_ON() to warn of intel_hpd_irq_event() from being called without mode_config.mutex held - suggested by Jani Nikula. Signed-off-by:Egbert Eich <eich@suse.de> Reviewed-by:
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Egbert Eich authored
This way it is possible to limit 're'-detect() of displays to connectors which have received an HPD event. v2: Reordered drm_i915_private: Move hpd_event_bits to hpd state tracking. v3: Fixed merge conflicts with previous patches. Signed-off-by:
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Jesse Barnes authored
We need to hold the rps lock around punit access. Reported-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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- 22 Apr, 2013 3 commits
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Kenneth Graunke authored
Now that we have function pointers, it's cleaner to just create a new per-platform PTE encoding function. This should be identical in behavior to the previous code. v2: Drop accidental inline keyword on hsw_pte_encode. Signed-off-by:
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Kenneth Graunke authored
On Bay Trail, bit 1 means "writeable by the GPU." Failing to set that means basically anything using the GPU will cause hangs. v2: Drop accidental inline keyword on byt_pte_encode. Signed-off-by:
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Kenneth Graunke authored
Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly different page table entry formats. Rather than polluting one function with generation checks, simply use a function pointer and set up the correct PTE encoding function at startup. v2: Move the gen6_gtt_pte_t typedef to i915_drv.h so that the function pointers and implementations have identical signatures. Also remove inline keyword on gen6_pte_encode. Both suggested by Jani Nikula. Signed-off-by:Jani Nikula <jani.nikula@linux.intel.com> Tested-by: Daniel Leung <daniel.leung@linux.intel.com> [v1] Signed-off-by:
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- 20 Apr, 2013 1 commit
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Ville Syrjälä authored
This allows unifying a bunch of the PLL calculations and whatnot. Signed-off-by:
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- 19 Apr, 2013 8 commits
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Jesse Barnes authored
Minor cleanup. Would be nice to use an enum for channel in the DPIO macros so we don't mix up pipes and channels, but that's for another patch. Signed-off-by:
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Damien Lespiau authored
We are trying to have more platform-orthogonal pieces of code. The DDI code shouldn't mention Haswell. v2: Fix the email address Signed-off-by:
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Ville Syrjälä authored
Shame on me for not putting the bit definitions next to the register definition in the first place. Signed-off-by:
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Paulo Zanoni authored
... inside haswell_get_pipe_config. Because there's one TRANS_DDI_FUNC_CTL register per CPU transcoder, not per pipe. This solves "unclaimed register" messages when booting with eDP only and using the i915.disable_power_well=1. Also fix a comment and remove an useless empty line. The error messages were caused by: commit 88adfff1 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Mar 28 10:42:01 2013 +0100 drm/i915: hw readout support for ->has_pch_encoders Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Paulo Zanoni authored
This fixes "unclaimed register" messages when booting with eDP only and i915.disable_power_well=1. The error messages were caused by: commit 0e8ffe1b Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Mar 28 10:42:00 2013 +0100 drm/i915: add hw state readout/checking for pipe_config Signed-off-by:
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Paulo Zanoni authored
This is bad news and shouldn't be happening. V2: Rebase. Signed-off-by:
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Paulo Zanoni authored
In this commit we enable both CPU and PCH FIFO underrun reporting and start reporting them. We follow a few rules: - after we receive one of these errors, we mask the interrupt, so we won't get an "interrupt storm" and we also won't flood dmesg; - at each mode set we enable the interrupts again, so we'll see each message at most once per mode set; - in the specific places where we need to ignore the errors, we completely mask the interrupts. The downside of this patch is that since we're completely disabling (masking) the interrupts instead of just not printing error messages, we will mask more than just what we want on IVB/HSW CPU interrupts (due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll also be masking PCH FIFO underruns for pipe B, because both are reported by SERR_INT, which has to be either completely enabled or completely disabled (in othe words, there's no way to disable/enable specific bits of GEN7_ERR_INT and SERR_INT). V2: Rename some functions and variables, downgrade messages to DRM_DEBUG_DRIVER and rebase. Signed-off-by: -
Jesse Barnes authored
In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the appropriate programming. We need to make sure that the tx lane reset occurs in both the full mode set and DPMS paths, so factor things out to allow that. v2: use different DPIO_DIVISOR values for VGA and DisplayPort v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values for all display interfaces v4: collapse with various updates v5: squash with crtc enable/pll enable bits v6: split out DP code (jbarnes) put phyready check under IS_VALLEYVIEW (jbarnes) remove unneeded check in 9xx pll div update (Jani) wrap VLV pll update call in IS_VALLEYVIEW (Jani) move port enable back to end of crtc enable (jbarnes) put phyready check under IS_VALLEYVIEW (jbarnes) v7: fix up conflicts against latest drm-intel-next-queued v8: use DPIO reg names, fix pipes (Jani) from mPhy_registers_VLV2_ww20p5 doc v9: update to latest info from driver enabling notes doc driver_vbios_notes_9 v10: fixup a bit of pipe/port confusion to allow eDP and HDMI to work simultaneously (Jesse) v11: use pll/port callbacks for DPIO port activity (Daniel) use separate VLV CRTC enable function (Daniel) move around port ready checks (Jesse) Signed-off-by:Pallavi G <pallavi.g@intel.com> Signed-off-by:
Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by:
Gajanan Bhat <gajanan.bhat@intel.com> Signed-off-by:
Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by:
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- 18 Apr, 2013 1 commit
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Jesse Barnes authored
This is a reset feature we don't actually need. Signed-off-by:
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