- 16 May, 2018 4 commits
-
-
Fuyun Liang authored
If hclge.ko has not been inserted, the value of ret always is zero in hnae3_register_ae_dev. If hclge.ko has been inserted, the value of ret is zero or non zero. Different execution ways have different results. It is confusing. The ae_dev which is initialized failed can be reinitialized when we remove hclge.ko and insert it again. For the case initializing client instance, it is just like the case initializing ae_dev. The main function of hnae3_register_ae_dev is adding the ae_dev to ad_dev list. Because adding ae_dev is always ok, we does not need to return any in this function. This patch changes the return type of hnae3_register_ae_dev from int to void. Signed-off-by:
Fuyun Liang <liangfuyun1@huawei.com> Signed-off-by:
Peng Li <lipeng321@huawei.com> Signed-off-by:
Salil Mehta <salil.mehta@huawei.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
-
Fuyun Liang authored
If the client instance is initializd failed, we do not need to uninit it. This patch adds a state check to check init state of client instance. Fixes: 38caee9d ("net: hns3: Add support of the HNAE3 framework") Signed-off-by:
-
Fuyun Liang authored
When initializing ae_dev failed during loading hclge.ko, the drvdata will be set to null. When removing hns3.ko, we get a null ae_dev. It causes the null pointer problem. This patch removes pci_set_drvdata from error handle of hclge_init_ae_dev to fix the bug, since pci_set_drvdata has been called in hns3_remove. Also, we do not need to uninit the ae_dev which is not initialized. And it may be the one which is initialized failed. Fixes: 46a3df9f ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support") Signed-off-by:
-
Fuyun Liang authored
When hnae3_unregister_ae_algo is called by PF, pci_disable_sriov is called. And then, hns3_remove is called by VF. We get deadlocked in this case. Since VF pci device is dependent on PF pci device, When PF pci device is removed, VF pci device must be removed. Also, To solve the deadlock problem, VF pci device should be removed before PF pci device is removed. This patch moves pci_enable/disable_sriov from hclge to hns3 to solve the deadlock problem. Also, we do not need to return EPROBE_DEFER in hnae3_register_ae_dev, because SRIOV is no longer enabled in the context calling hnae3_register_ae_dev. Mutex_trylock can be replaced with mutex_lock. Fixes: 424eb834 ("net: hns3: Unified HNS3 {VF|PF} Ethernet Driver for hip08 SoC") Signed-off-by:
-
- 15 May, 2018 21 commits
-
-
David S. Miller authored
Alexandre Belloni says: ==================== Microsemi Ocelot Ethernet switch support This series adds initial support for the Microsemi Ethernet switch present on Ocelot SoCs. This only has bridging (and STP) support for now and it uses the switchdev framework. Coming features are VLAN filtering, link aggregation, IGMP snooping. The switch can also be connected to an external CPU using PCIe. Also, support for integration on other SoCs will be submitted. The ocelot dts changes are here for reference and should probably go through the MIPS tree once the bindings are accepted. Changes in v3: - Collected Reviewed-by * Switchdev driver: - Fixed two issues reported by kbuild - Modified ethtool statistics to support different layoiut on different chips and take care of counter overflow Changes in v2: - Dropped Microsemi Ocelot PHY support * MIIM driver: - Documented interrupts bindings - Moved the driver to drivers/net/phy/ - Removed unused mutex - Removed MDIO bus scanning * Switchdev driver: - Changed compatible to mscc,vsc7514-switch - Removed unused header inclusion - Factorized MAC table selection in ocelot_mact_select() - Disable the port in ocelot_port_stop() - Fixed the smatch endianness warnings - int to unsinged int where necessary - Removed VID handling for the FDB it has been reworked anyway and will be submitted with VLAN support - Fixed up unused cases in ocelot_port_attr_set() - Added a loop to register all the IO register spaces - the ports are now in an ethernet-ports node I've tried switching to NAPI but this is not working well, mainly because the only way to disable interrupts is to actually mask them in the interrupt controller (it is not possible to tell the switch to stop generating interrupts). ==================== Signed-off-by: -
Alexandre Belloni authored
Add myself as a maintainer for the Microsemi Ethernet switches. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
-
Alexandre Belloni authored
Add a driver for Microsemi Ocelot Ethernet switch support. This makes two modules: mscc_ocelot_common handles all the common features that doesn't depend on how the switch is integrated in the SoC. Currently, it handles offloading bridging to the hardware. ocelot_io.c handles register accesses. This is unfortunately needed because the register layout is packed and then depends on the number of ports available on the switch. The register definition files are automatically generated. ocelot_board handles the switch integration on the SoC and on the board. Frame injection and extraction to/from the CPU port is currently done using register accesses which is quite slow. DMA is possible but the port is not able to absorb the whole switch bandwidth. Signed-off-by:
-
Alexandre Belloni authored
DT bindings for the Ethernet switch found on Microsemi Ocelot platforms. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
-
Alexandre Belloni authored
Add a driver for the Microsemi MII Management controller (MIIM) found on Microsemi SoCs. On Ocelot, there are two controllers, one is connected to the internal PHYs, the other one can communicate with external PHYs. Reviewed-by:
-
Alexandre Belloni authored
DT bindings for the Microsemi MII Management Controller found on Microsemi SoCs Reviewed-by:
-
David S. Miller authored
Marcelo Ricardo Leitner says: ==================== sctp: Introduce sctp_flush_ctx This struct will hold all the context used during the outq flush, so we don't have to pass lots of pointers all around. Checked on x86_64, the compiler inlines all these functions and there is no derreference added because of the struct. This patchset depends on 'sctp: refactor sctp_outq_flush' Changes since v1: - updated to build on top of v2 of 'sctp: refactor sctp_outq_flush' Changes since v2: - fixed a rebase issue which reverted a change in patch 2. - rebased on v3 of 'sctp: refactor sctp_outq_flush' ==================== Signed-off-by: -
Marcelo Ricardo Leitner authored
A collection of fixups from previous patches, left for later to not introduce unnecessary changes while moving code around. Signed-off-by:
Marcelo Ricardo Leitner <marcelo.leitner@gmail.com> Signed-off-by:
-
Marcelo Ricardo Leitner authored
Pre-compute these so the compiler won't reload them (due to no-strict-aliasing). Changes since v2: - Do not replace a return with a break in sctp_outq_flush_data Signed-off-by:
-
Marcelo Ricardo Leitner authored
With this struct we avoid passing lots of variables around and taking care of updating the current transport/packet. Signed-off-by:
-
David S. Miller authored
Marcelo Ricardo Leitner says: ==================== sctp: refactor sctp_outq_flush Currently sctp_outq_flush does many different things and arguably unrelated, such as doing transport selection and outq dequeueing. This patchset refactors it into smaller and more dedicated functions. The end behavior should be the same. The next patchset will rework the function parameters. Changes since v1: - fix build issues on patches 3 and 4, and updated 5 and 8 because of it. Changes since v2: - fixed panic if building with just up to patch 3 applied ==================== Signed-off-by: -
Marcelo Ricardo Leitner authored
Remove an inner one, which tended to be error prone due to the cascading and it can be replaced by a simple if (). Rework the outer one so that the actual flush code is not inside it. Now we first validate if we can or cannot send data, return if not, and then the flush code. Suggested-by:
Xin Long <lucien.xin@gmail.com> Signed-off-by:
-
Marcelo Ricardo Leitner authored
Retransmissions may be triggered when in user context, so lets make use of gfp. Signed-off-by:
-
Marcelo Ricardo Leitner authored
To the new sctp_outq_flush_transports. Comment on Nagle is outdated and removed. Nagle is performed earlier, while checking if the chunk fits the packet: if the outq length is not enough to fill the packet, it returns SCTP_XMIT_DELAY. So by when it gets to sctp_outq_flush_transports, it has to go through all enlisted transports. Signed-off-by:
-
Marcelo Ricardo Leitner authored
To the new sctp_outq_flush_data. Again, smaller functions and with well defined objectives. Signed-off-by:
-
Marcelo Ricardo Leitner authored
This patch renames current sctp_outq_flush_rtx to __sctp_outq_flush_rtx and create a new sctp_outq_flush_rtx, with the code that was on sctp_outq_flush. Again, the idea is to have functions with small and defined objectives. Yes, there is an open-coded path selection in the now sctp_outq_flush_rtx. That is kept as is for now because it may be very different when we implement retransmission path selection algorithms for CMT-SCTP. Signed-off-by:
-
Marcelo Ricardo Leitner authored
Named sctp_outq_flush_ctrl and, with that, keep the contexts contained. One small fix embedded is the reset of one_packet at every iteration. This allows bundling of some control chunks in case they were preceeded by another control chunk that cannot be bundled. Other than this, it has the same behavior. Changes since v2: - Fixed panic reported by kbuild test robot if building with only up to this patch applied, due to bad parameter to sctp_outq_select_transport and by not initializing packet after calling sctp_outq_flush_ctrl. Signed-off-by:
-
Marcelo Ricardo Leitner authored
We had two spots doing such complex operation and they were very close to each other, a bit more tailored to here or there. This patch unifies these under the same function, sctp_outq_select_transport, which knows how to handle control chunks and original transmissions (but not retransmissions). Signed-off-by:
-
Marcelo Ricardo Leitner authored
Factor out the code for generating singletons. It's used only once, but helps to keep the context contained. The const variables are to ease the reading of subsequent calls in there. Signed-off-by:
-
Kumar Sanghvi authored
Adds support for matching flows based on tunnel VNI value. Introduces fw APIs for allocating/removing MPS entries related to encapsulation. And uses the same while adding/deleting filters for offloading flows based on tunnel VNI match. Signed-off-by:
Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by:
Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by:
-
Jose Abreu authored
I'm offering to be a co-maintainer for stmmac driver. As per discussion with Alexandre, I will arrange to get STM32 boards to test patches in GMAC version 3.x and 4.1. I also have HW to test GMAC version 5. Looking forward to contribute to net-dev! Signed-off-by:
Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
-
- 14 May, 2018 15 commits
-
-
Arjun Vynipadath authored
We no longer require a check for cxgb4 to be MASTER when configuring SRIOV, It was required when we had module parameter to instantiate vf. Signed-off-by:
Arjun Vynipadath <arjun@chelsio.com> Signed-off-by:
Casey Leedom <leedom@chelsio.com> Signed-off-by:
-
Petr Machata authored
When resolving a path that the packet will take after being encapsulated in mirror-to-gretap scenarios, one of the devices en route could be a LAG. In that case, mirror to first up slave that corresponds to a front panel port. Signed-off-by:
Petr Machata <petrm@mellanox.com> Signed-off-by:
Ido Schimmel <idosch@mellanox.com> Signed-off-by:
-
Hernán Gonzalez authored
Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...)). drivers/net/ethernet/ti/cpts.c:567:9-16: WARNING: ERR_CAST can be used with cpts->refclk Generated by: scripts/coccinelle/api/err_cast.cocci Signed-off-by:
Hernán Gonzalez <hernan@vanguardiasur.com.ar> Signed-off-by:
-
Marcelo Ricardo Leitner authored
Currently, when the rule is not to be exclusively executed by the hardware, extack is not passed along and offloading failures don't get logged. The idea was that hardware failures are okay because the rule will get executed in software then and this way it doesn't confuse unware users. But this is not helpful in case one needs to understand why a certain rule failed to get offloaded. Considering it may have been a temporary failure, like resources exceeded or so, reproducing it later and knowing that it is triggering the same reason may be challenging. The ultimate goal is to improve Open vSwitch debuggability when using flower offloading. This patch adds a new flag to enable verbose logging. With the flag set, extack will be passed to the driver, which will be able to log the error. As the operation itself probably won't fail (not because of this, at least), current iproute will already log it as a Warning. The flag is generic, so it can be reused later. No need to restrict it just for HW offloading. The command line will follow the syntax that tc-ebpf already uses, tc ... [ verbose ] ... , and extend its meaning. For example: # ./tc qdisc add dev p7p1 ingress # ./tc filter add dev p7p1 parent ffff: protocol ip prio 1 \ flower verbose \ src_mac ed:13:db:00:00:00 dst_mac 01:80:c2:00:00:d0 \ src_ip 56.0.0.0 dst_ip 55.0.0.0 action drop Warning: TC offload is disabled on net device. # echo $? 0 # ./tc filter add dev p7p1 parent ffff: protocol ip prio 1 \ flower \ src_mac ff:13:db:00:00:00 dst_mac 01:80:c2:00:00:d0 \ src_ip 56.0.0.0 dst_ip 55.0.0.0 action drop # echo $? 0 Signed-off-by:
-
David S. Miller authored
Chen-Yu Tsai says: ==================== net: stmmac: dwmac-sun8i: Support R40 This is a resend of the patches for net-next split out from my R40 Ethernet support v2 series, as requested by David Miller. The arm-soc bits will follow, once I rework the A64 system controller compatible. Patches 1, 2, and 3 clean up the dwmac-sun8i binding. Patch 4 adds device tree binding for Allwinner R40's Ethernet controller. Patch 5 converts regmap access of the syscon region in the dwmac-sun8i driver to regmap_field, in anticipation of different field widths on the R40. Patch 6 introduces custom plumbing in the dwmac-sun8i driver to fetch a regmap from another device, by looking up said device via a phandle, then getting the regmap associated with that device. Patch 7 adds support for different or absent TX/RX delay chain ranges to the dwmac-sun8i driver. Patch 8 adds support for the R40's ethernet controller. Excerpt from original cover letter: Changes since v1: - Default to fetching regmap from device pointed to by syscon phandle, and falling back to syscon API if that fails. - Dropped .syscon_from_dev field in device data as a result of the previous change. - Added a large comment block explaining the first change. - Simplified description of syscon property in sun8i-dwmac binding. - Regmap now only exposes the EMAC/GMAC register, but retains the offset within its address space. - Added patches for A64, which reuse the same sun8i-dwmac changes. This series adds support for the DWMAC based Ethernet controller found on the Allwinner R40 SoC. The controller is either a DWMAC clone or DWMAC core with its registers rearranged. This is already supported by the dwmac-sun8i driver. The glue layer control registers, unlike other sun8i family SoCs, is not in the system controller region, but in the clock control unit, like with the older A20 and A31 SoCs. While we reuse the bindings for dwmac-sun8i using a syscon phandle reference, we need some custom plumbing for the clock driver to export a regmap that only allows access to the GMAC register to the dwmac-sun8i driver. An alternative would be to allow drivers to register custom syscon devices with their own regmap and locking. ==================== Signed-off-by: -
Chen-Yu Tsai authored
The Allwinner R40 SoC has the EMAC controller supported by dwmac-sun8i. It is named "GMAC", while EMAC refers to the 10/100 Mbps Ethernet controller supported by sun4i-emac. The controller is the same, but the R40 has the glue layer controls in the clock control unit (CCU), with a reduced RX delay chain, and no TX delay chain. This patch adds support for it using the framework laid out by previous patches to map the differences. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
-
Chen-Yu Tsai authored
On the R40 SoC, the RX delay chain only has a range of 0~7 (hundred picoseconds), instead of 0~31. Also the TX delay chain is completely absent. This patch adds support for different ranges by adding per-compatible maximum values in the variant data. A maximum of 0 indicates that the delay chain is not supported or absent. Signed-off-by:
-
Chen-Yu Tsai authored
On the Allwinner R40 SoC, the "GMAC clock" register is in the CCU address space. Using a standard syscon to access it provides no coordination with the CCU driver for register access. Neither does it prevent this and other drivers from accessing other, maybe critical, clock control registers. On other SoCs, the register is in the "system control" address space, which might also contain controls for mapping SRAM to devices or the CPU. This hardware has the same issues. Instead, for these types of setups, we let the device containing the control register create a regmap tied to it. We can then get the device from the existing syscon phandle, and retrieve the regmap with dev_get_regmap(). Signed-off-by:
-
Chen-Yu Tsai authored
On the Allwinner R40, the "GMAC clock" register is located in the CCU block, at a different register address than the other SoCs that have it in the "system control" block. This patch converts the use of regmap to regmap_field for mapping and accessing the syscon register, so we can have the register address in the variants data, and not in the actual register manipulation code. This patch only converts regmap_read() and regmap_write() calls to regmap_field_read() and regmap_field_write() calls. There are some places where it might make sense to switch to regmap_field_update_bits(), but this is not done here to keep the patch simple. Signed-off-by:
-
Chen-Yu Tsai authored
The Allwinner R40 SoC has the EMAC controller supported by dwmac-sun8i. It is named "GMAC", while EMAC refers to the 10/100 Mbps Ethernet controller supported by sun4i-emac. The controller is the same, but the R40 has the glue layer controls in the clock control unit (CCU), with a reduced RX delay chain, and no TX delay chain. This patch adds the R40 specific bits to the dwmac-sun8i binding. Signed-off-by:
-
Chen-Yu Tsai authored
The syscon property is used to point to the device that holds the glue layer control register known as the "EMAC (or GMAC) clock register". We do not need to explicitly list what compatible strings are needed, as this information is readily available in the user manuals. Also the "syscon" device type is more of an implementation detail. There are many ways to access a register not in a device's address range, the syscon interface being the most generic and unrestricted one. Simplify the description so that it says what it is supposed to describe. Signed-off-by:
-
Chen-Yu Tsai authored
The A83T syscon compatible was appended to the syscon compatibles list, instead of inserted in to preserve the ordering. Move it to the proper place to keep the list sorted. Signed-off-by:
-
Chen-Yu Tsai authored
The clock delay chains found in the glue layer for dwmac-sun8i are only used with RGMII PHYs. They are not intended for non-RGMII PHYs, such as MII external PHYs or the internal PHY. Also, a recent SoC has a smaller range of possible values for the delay chain. This patch reformats the delay chain section of the device tree binding to make it clear that the delay chains only apply to RGMII PHYs, and make it easier to add the R40-specific bits later. Signed-off-by:
-
David S. Miller authored
Vivien Didelot says: ==================== net: dsa: mv88e6xxx: remove Global 1 setup The mv88e6xxx driver is still writing arbitrary registers at setup time, e.g. priority override bits. Add ops for them and provide specific setup functions for priority and stats before getting rid of the erroneous mv88e6xxx_g1_setup code, as previously done with Global 2. ==================== Signed-off-by: -
Vivien Didelot authored
Now that the Global 1 specific setup function only setup the statistics unit, kill it in favor of a mv88e6xxx_stats_setup function. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
-
