1. 16 Jun, 2017 19 commits
    • Rob Clark's avatar
      drm/msm: update generated headers · 52260ae4
      Rob Clark authored
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      52260ae4
    • Rob Clark's avatar
      drm/msm: remove address-space id · 8432a903
      Rob Clark authored
      Now that the msm_gem supports an arbitrary number of vma's, we no longer
      need to assign an id (index) to each address space.  So rip out the
      associated code.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      8432a903
    • Rob Clark's avatar
      drm/msm: support for an arbitrary number of address spaces · 4b85f7f5
      Rob Clark authored
      It means we have to do a list traversal where we once had an index into
      a table.  But the list will normally have one or two entries.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      4b85f7f5
    • Rob Clark's avatar
      drm/msm: refactor how we handle vram carveout buffers · f4839bd5
      Rob Clark authored
      Pull some of the logic out into msm_gem_new() (since we don't need to
      care about the imported-bo case), and don't defer allocating pages.  The
      latter is generally a good idea, since if we are using VRAM carveout to
      allocate contiguous buffers (ie. no IOMMU), the allocation is more
      likely to fail.  So failing at allocation time is a more sane option.
      Plus this simplifies things in the next patch.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      f4839bd5
    • Rob Clark's avatar
      drm/msm: pass address-space to _get_iova() and friends · 8bdcd949
      Rob Clark authored
      No functional change, that will come later.  But this will make it
      easier to deal with dynamically created address spaces (ie. per-
      process pagetables for gpu).
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      8bdcd949
    • Rob Clark's avatar
      drm/msm/mdp4+5: move aspace/id to base class · f59f62d5
      Rob Clark authored
      Before we can shift to passing the address-space object to _get_iova(),
      we need to fix a few places (dsi+fbdev) that were hard-coding the adress
      space id.  That gets somewhat easier if we just move these to the kms
      base class.
      
      Prep work for next patch.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      f59f62d5
    • Rob Clark's avatar
      drm/msm/mdp5: kill pipe_lock · aa7cd242
      Rob Clark authored
      It serves no purpose, things should be sufficiently synchronized already
      by atomic framework.  And it is somewhat awkward to be holding a spinlock
      when msm_gem_iova() is going to start needing to grab a mutex.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      aa7cd242
    • Rob Clark's avatar
      drm/msm: fix locking inconsistency for gpu->hw_init() · cb1e3818
      Rob Clark authored
      Most, but not all, paths where calling the with struct_mutex held.  The
      fast-path in msm_gem_get_iova() (plus some sub-code-paths that only run
      the first time) was masking this issue.
      
      So lets just always hold struct_mutex for hw_init().  And sprinkle some
      WARN_ON()'s and might_lock() to avoid this sort of problem in the
      future.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      cb1e3818
    • Jordan Crouse's avatar
      drm/msm: Remove memptrs->wptr · 42a105e9
      Jordan Crouse authored
      memptrs->wptr seems to be unused. Remove it to avoid
      confusing the upcoming preemption code.
      Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      42a105e9
    • Jordan Crouse's avatar
      drm/msm: Add a struct to pass configuration to msm_gpu_init() · 5770fc7a
      Jordan Crouse authored
      The amount of information that we need to pass into msm_gpu_init()
      is steadily increasing, so add a new struct to stabilize the function
      call and make it easier to add new configuration down the line.
      Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      5770fc7a
    • Jordan Crouse's avatar
      drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA · 49fd08ba
      Jordan Crouse authored
      Modify the 'pad' member of struct drm_msm_gem_info to 'flags'. If the
      user sets 'flags' to non-zero it means that they want a IOVA for the
      GEM object instead of a mmap() offset. Return the iova in the 'offset'
      member.
      Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
      [robclark: s/hint/flags in commit msg]
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      49fd08ba
    • Jordan Crouse's avatar
      drm/msm: Remove idle function hook · e895c7bd
      Jordan Crouse authored
      There isn't any generic code that uses ->idle so remove it.
      Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      e895c7bd
    • Jordan Crouse's avatar
      drm/msm: Remove DRM_MSM_NUM_IOCTLS · 167b606a
      Jordan Crouse authored
      The ioctl array is sparsely populated but the compiler will make sure
      that it is sufficiently sized for all the values that we have so we
      can safely use ARRAY_SIZE() instead of having a constantly changing
      #define in the uapi header.
      Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      167b606a
    • Jordan Crouse's avatar
      drm/msm: gpu: Enable zap shader for A5XX · 7c65817e
      Jordan Crouse authored
      The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
      only render to buffers that are marked as secure and inaccessible
      to the kernel and user through a series of hardware protections. In
      practice secure mode is used to draw things like a UI on a secure
      video frame.
      
      In order to switch out of secure mode the GPU executes a special
      shader that clears out the GMEM and other sensitve registers and
      then writes a register. Because the kernel can't be trusted the
      shader binary is signed and verified and programmed by the
      secure world. To do this we need to read the MDT header and the
      segments from the firmware location and put them in memory and
      present them for approval.
      
      For targets without secure support there is an out: if the
      secure world doesn't support secure then there are no hardware
      protections and we can freely write the SECVID_TRUST register from
      the CPU. We don't have 100% confidence that we can query the
      secure capabilities at run time but we have enough calls that
      need to go right to give us some confidence that we're at least doing
      something useful.
      
      Of course if we guess wrong you trigger a permissions violation
      which usually ends up in a system crash but thats a problem
      that shows up immediately.
      
      [v2: use child device per Bjorn]
      [v3: use generic MDT loader per Bjorn]
      [v4: use managed dma functions and ifdefs for the MDT loader]
      [v5: Add depends for QCOM_MDT_LOADER]
      Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
      Acked-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      [robclark: fix Kconfig to use select instead of depends + #if IS_ENABLED()]
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      7c65817e
    • Dave Airlie's avatar
      BackMerge tag 'v4.12-rc5' into drm-next · 925344cc
      Dave Airlie authored
      Linux 4.12-rc5 for nouveau fixes
      925344cc
    • Dave Airlie's avatar
      Merge tag 'imx-drm-next-2017-06-08' of git://git.pengutronix.de/git/pza/linux into drm-next · a6821698
      Dave Airlie authored
      imx-drm: cleanups and YUV 4:2:0 memory read/write reduction support
      
      - Remove counter load enable form PRE, which has no effect.
      - Add support for setting the double read/write reduction flag in channel
        parameter memory. This can be used to save some memory bandwidth when
        capturing in YUV 4:2:0 chroma subsampled formats.
      - Allocate DMA channel structures as needed, most of the 64 channels are
        unused or even reserved.
      - Remove unused interrupt busy waiting routine.
      - Set VDIC field order for both AUTO and MAN inputs simultaneously as
        both can't be active at the same time.
      
      * tag 'imx-drm-next-2017-06-08' of git://git.pengutronix.de/git/pza/linux:
        gpu: ipu-v3: vdic: include AUTO field order bit in ipu_vdi_set_field_order
        gpu: ipu-v3: remove interrupt busy waiting routine
        gpu: ipu-v3: allocate ipuv3_channels as needed
        gpu: ipu-v3: Add support for double read/write reduction
        gpu: ipu-v3: prg: remove counter load enable
      a6821698
    • Dave Airlie's avatar
      Merge tag 'drm-fsl-dcu-for-v4.13' of http://git.agner.ch/git/linux-drm-fsl-dcu into drm-next · 033fd325
      Dave Airlie authored
      some fsl-dcu cleanups
      
      * tag 'drm-fsl-dcu-for-v4.13' of http://git.agner.ch/git/linux-drm-fsl-dcu:
        drm/fsl-dcu: use new drm_atomic_helper_shutdown
        drm/fsl-dcu: implement irq_preinstall/uninstall callbacks
        drm/fsl: Drop drm_vblank_cleanup
      033fd325
    • Dave Airlie's avatar
      Merge branch 'drm/next/du' of git://linuxtv.org/pinchartl/media into drm-next · 202dfa08
      Dave Airlie authored
      The series interleaves DRM and V4L2 patches due to dependencies between the R-
      Car DU and VSP drivers. Mauro has acked all the V4L2 patches to go through
      your tree, and they don't conflict with anything queued for v4.13 in his tree.
      If I need to send any conflicting patches through Mauro's tree for v4.13, I'll
      make sure to base them on this branch.
      
      * 'drm/next/du' of git://linuxtv.org/pinchartl/media:
        drm: rcar-du: Map memory through the VSP device
        v4l: vsp1: Add API to map and unmap DRM buffers through the VSP
        v4l: vsp1: Map the DL and video buffers through the proper bus master
        v4l: rcar-fcp: Add an API to retrieve the FCP device
        v4l: rcar-fcp: Don't get/put module reference
        drm: rcar-du: Register a completion callback with VSP1
        v4l: vsp1: Extend VSP1 module API to allow DRM callbacks
        v4l: vsp1: Postpone frame end handling in event of display list race
        drm: rcar-du: Arm the page flip event after queuing the page flip
      202dfa08
    • Dave Airlie's avatar
      Merge tag 'sunxi-drm-for-4.13' of... · 7249e3d6
      Dave Airlie authored
      Merge tag 'sunxi-drm-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next
      
      sun4i-drm changes for 4.13
      
      An unusually big pull request for this merge window, with three notable
      features:
        - V3s display engine support. This is especially notable because it uses
          a different display engine used on the newer Allwinner SoCs (H3, A64
          and the likes) that will be quite easily supported now.
        - HDMI support for the old Allwinner SoCs. This is enabled only on the
          A10s for now, but should be really easy to extend to deal with A10, A20
          and A31
        - Preliminary work to deal with dual-pipeline SoCs (A10, A20, A31, H3,
          etc.). It currently ignores the second pipeline, but we can use the
          dual-pipelines bindings. This will be useful to enable the display
          pipeline while we work on the dual-pipeline.
      
      * tag 'sunxi-drm-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (27 commits)
        drm/sun4i: Add compatible for the A10s pipeline
        drm/sun4i: Add HDMI support
        dt-bindings: display: sun4i: Add allwinner,tcon-channel property
        dt-bindings: display: sun4i: Add HDMI display bindings
        drm/sun4i: Ignore the generic connectors for components
        drm/sun4i: tcon: multiply the vtotal when not in interlace
        drm/sun4i: tcon: Change vertical total size computation inconsistency
        drm/sun4i: tcon: Fix tcon channel 1 backporch calculation
        drm/sun4i: tcon: Switch mux on only for composite
        drm/sun4i: tcon: Move the muxing out of the mode set function
        drm/sun4i: tcon: Add channel debug
        drm/sun4i: tcon: add support for V3s TCON
        drm/sun4i: Add compatible string for V3s display engine
        drm/sun4i: add support for Allwinner DE2 mixers
        drm/sun4i: add a Kconfig option for sun4i-backend
        drm/sun4i: abstract a engine type
        drm/sun4i: return only planes for layers created
        dt-bindings: add bindings for DE2 on V3s SoC
        drm/sun4i: backend: Clarify sun4i_backend_layer_enable debug message
        drm/sun4i: Set TCON clock inside sun4i_tconX_mode_set
        ...
      7249e3d6
  2. 15 Jun, 2017 21 commits