1. 27 Aug, 2019 1 commit
    • Xiaojie Yuan's avatar
      drm/amdgpu: add dummy read for some GCVM status registers · 53499173
      Xiaojie Yuan authored
      The GRBM register interface is now capable of bursting 1 cycle per
      register wr->wr, wr->rd much faster than previous muticycle per
      transaction done interface.  This has caused a problem where status
      registers requiring HW to update have a 1 cycle delay, due to the
      register update having to go through GRBM.
      
      SW may operate on an incorrect value if they write a register and
      immediately check the corresponding status register.
      
      Registers requiring HW to clear or set fields may be delayed by 1 cycle.
      For example,
      
      1. write VM_INVALIDATE_ENG0_REQ mask = 5a
      2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
          a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete
      3. write VM_INVALIDATE_ENG0_REQ mask = 5a
      4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
          a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0
          b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because
             the remote GRBM h/w register takes one extra cycle to be cleared
          c. In this case, SW will see a false ACK if they exit on first read
      
      Affected registers (only GC variant)  |  Recommended Dummy Read
      --------------------------------------+----------------------------
      VM_INVALIDATE_ENG*_ACK                |  VM_INVALIDATE_ENG*_REQ
      VM_L2_STATUS                          |  VM_L2_STATUS
      VM_L2_PROTECTION_FAULT_STATUS         |  VM_L2_PROTECTION_FAULT_STATUS
      VM_L2_PROTECTION_FAULT_ADDR_HI/LO32   |  VM_L2_PROTECTION_FAULT_ADDR_HI/LO32
      VM_L2_IH_LOG_BUSY                     |  VM_L2_IH_LOG_BUSY
      MC_VM_L2_PERFCOUNTER_HI/LO            |  MC_VM_L2_PERFCOUNTER_HI/LO
      ATC_L2_PERFCOUNTER_HI/LO              |  ATC_L2_PERFCOUNTER_HI/LO
      ATC_L2_PERFCOUNTER2_HI/LO             |  ATC_L2_PERFCOUNTER2_HI/LO
      Signed-off-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
      Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      53499173
  2. 23 Aug, 2019 39 commits