- 08 Oct, 2018 4 commits
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Miquel Raynal authored
With the current implementation, the complete() in the IRQ handler is supposed to be called only if the register status has one or the other RDY bit set. Other events might trigger an interrupt as well if enabled, but should not end-up with a complete() call. For this purpose, the code was checking if the other bits were set, in this case complete() was not called. This is wrong as two events might happen in a very tight time-frame and if the NDSR status read reports two bits set (eg. RDY(0) and RDDREQ) at the same time, complete() was not called. This logic would lead to timeouts in marvell_nfc_wait_op() and has been observed on PXA boards (NFCv1) in the Hamming write path. Fixes: 02f26ecf ("mtd: nand: add reworked Marvell NAND controller driver") Cc: stable@vger.kernel.org Reported-by:
Daniel Mack <daniel@zonque.org> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Tested-by:
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Masahiro Yamada authored
NAND devices need additional data area (OOB) for error correction, but it is also used for Bad Block Marker (BBM). In many cases, the first byte in OOB is used for BBM, but the location actually depends on chip vendors. The NAND controller should preserve the precious BBM to keep track of bad blocks. In Denali IP, the SPARE_AREA_SKIP_BYTES register is used to specify the number of bytes to skip from the start of OOB. The ECC engine will automatically skip the specified number of bytes when it gets access to OOB area. The same value for SPARE_AREA_SKIP_BYTES should be used between firmware and the operating system if you intend to use the NAND device across the control hand-off. In fact, the current denali.c code expects firmware to have already set the SPARE_AREA_SKIP_BYTES register, then reads the value out. If no firmware (or bootloader) has initialized the controller, the register value is zero, which is the default after power-on-reset. In other words, the Linux driver cannot initialize the controller by itself. Some possible solutions are: [1] Add a DT property to specify the skipped bytes in OOB [2] Associate the preferred value with compatible [3] Hard-code the default value in the driver My first attempt was [1], but in the review process, [3] was suggested as a counter-implementation. (https://lore.kernel.org/patchwork/patch/983055/) The default value 8 was chosen to match to the boot ROM of the UniPhier platform. The preferred value may vary by platform. If so, please trade up to a different solution. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by:
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Colin Ian King authored
Trivial fix to spelling mistake struct field name, rename it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Miquel Raynal authored
Now that most of the raw NAND API is consistent and has almost all its helpers and hooks using a single nand_chip object instead of an mtd_info one (or both), let's do the same cleanup in the raw NAND vendors drivers. Apply this change to the Toshiba driver so that the internal helper to retrieve the ECC status does only take a nand_chip object. Suggested-by:
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- 03 Oct, 2018 36 commits
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Boris Brezillon authored
Currently, the selection of ECC byte ordering for software hamming is done at compilation time, which doesn't make sense when ECC byte calculation is done in hardware and byte ordering is forced by the hardware engine. In this case, only the correction is done in software and we want to force the byte-ordering no matter the value of CONFIG_MTD_NAND_ECC_SMC. This is typically the case for the FSMC (Smart Media ordering), TMIO and TXX9NDFMC (regular byte ordering) blocks. For all other use cases (pure software implementation, SM FTL and nandecctest), we keep selecting the byte ordering based on the CONFIG_MTD_NAND_ECC_SMC value. It might not be ideal for SM FTL (I'd expect Smart Media ordering to be employed by the Smart Media FTL), but this option doesn't seem to be enabled in the existing _defconfig, so I can't tell setting sm_order to true is the right choice. Signed-off-by:
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Nathan Chancellor authored
Clang warns when one enumerated type is converted implicitly to another: drivers/mtd/nand/raw/sh_flctl.c:483:46: warning: implicit conversion from enumeration type 'enum dma_transfer_direction' to different enumeration type 'enum dma_data_direction' [-Wenum-conversion] flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM) > 0) ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~ drivers/mtd/nand/raw/sh_flctl.c:542:46: warning: implicit conversion from enumeration type 'enum dma_transfer_direction' to different enumeration type 'enum dma_data_direction' [-Wenum-conversion] flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV) > 0) ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~ 2 warnings generated. Use the proper enums from dma_data_direction to satisfy Clang. DMA_MEM_TO_DEV = DMA_TO_DEVICE = 1 DMA_DEV_TO_MEM = DMA_FROM_DEVICE = 2 Reported-by:Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Reviewed-by:
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Janusz Krzysztofik authored
In its current shape, the driver sets data port direction before each byte read/write operation, even during multi-byte transfers. Improve performance of the driver by setting the port direction only when needed. This optimisation will become particularly important as soon as planned conversion of the driver to GPIO API for data I/O will be implemented. Reviewed-by:
Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by:
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Janusz Krzysztofik authored
Introduce a driver private structure and allocate it on device probe. Use it for storing nand_chip structure, GPIO descriptors prevoiusly stored in static variables as well as io_base pointer previously passed as nand controller data or platform driver data. Subsequent patches may populate the structure with more members as needed. Signed-off-by:
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Janusz Krzysztofik authored
Fix a bug where parent device symlinks aren't shown in sysfs. While at it, make use of the default owner set by mtdcore. Signed-off-by:
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Janusz Krzysztofik authored
Now as Amstrad Delta board - the only user of this driver - provides GPIO lookup tables, switch from GPIO numbers to GPIO descriptors and use the table to locate required GPIO pins. Declare static variables for storing GPIO descriptors and replace gpio_ function calls with their gpiod_ equivalents. Pin naming used by the driver should be followed while respective GPIO lookup table is initialized by a board init code. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Gustavo A. R. Silva authored
There is a potential execution path in which function of_find_compatible_node() returns NULL. In such a case, we end up having a NULL pointer dereference when accessing pointer *nfc_np* in function of_clk_get(). So, we better don't take any chances and fix this by null checking pointer *nfc_np* before calling of_clk_get(). Addresses-Coverity-ID: 1473052 ("Dereference null return value") Fixes: f88fc122 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by:
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Konstantin Porotchkin authored
Add support for two new layouts: 8kiB pages NAND chips, requesting either 4 or 8 bit of correctability per 512B step. Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Reviewed-by:
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Marcel Ziswiler authored
This patch enables support to read the ECC level from the NAND flash using ESMT SLC NAND ID byte 5 information as documented e.g. in the following data sheet: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F59L1G81LA(2Y).pdfSigned-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by:
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Marcel Ziswiler authored
Reorder NAND manufacturer IDs for clarity. Signed-off-by:
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Boris Brezillon authored
This moves JEDEC related code to nand_jedec.c and JEDEC related struct/macros to include/linux/mtd/jedec.h. Signed-off-by:
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Boris Brezillon authored
This moves ONFI related code to nand_onfi.c and ONFI related struct/macros to include/linux/mtd/onfi.h. Signed-off-by:
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Boris Brezillon authored
Allows us to move a few hundred lines of deprecated code out of the core file which is quite big. Signed-off-by:
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Boris Brezillon authored
A lot of things defined in rawnand.h should not be exposed to NAND controller drivers and should only be shared by core files. Create the drivers/mtd/nand/raw/internals.h header to store such definitions, and move all private defs to this header. Also remove EXPORT_SYMBOLS() on functions that are not supposed to be exposed. Signed-off-by:
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Boris Brezillon authored
onfi_get_async_timing_mode() is only used in one place inside nand_base.c. Let's inline the code and kill the helper. Signed-off-by:
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Boris Brezillon authored
platform_nand_xxx definitions are just used by the plat_nand driver. Let's move those definitions out of the core/driver-agnostic rawnand.h header. Signed-off-by:
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Boris Brezillon authored
Those definitions are not used, let's remove them. Signed-off-by:
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Boris Brezillon authored
There's already a forward declaration of nand_chip at the beginning of the file. Get rid of this one. Signed-off-by:
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Boris Brezillon authored
nand_scan[with_ids]() have been moved at the end of the file. We can now get rid of of the nand_flash_dev forward declaration. Signed-off-by:
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Boris Brezillon authored
Move nand_scan[_with_ids]() and nand_wait_ready() at the end of the file where all function prototype lies. This will also allow us to get rid of the nand_flash_dev forward declaration. Signed-off-by:
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Boris Brezillon authored
The wait timeouts and delays are directly extracted from the NAND timings and ->chip_delay is only used in legacy path, so let's move it to the nand_legacy struct to make it clear. Signed-off-by:
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Boris Brezillon authored
Those hooks should be replaced by a proper ->exec_op() implementation. Move them to the nand_legacy struct to make it clear. Signed-off-by:
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Boris Brezillon authored
The ->erase() hook have been overloaded by some drivers for bad reasons: either the driver was not fitting in the NAND framework and should have been an MTD driver (docg4), or the driver uses a specific path for the ERASE operation (denali), instead of implementing it generically. In any case, we should discourage people from overloading this method and encourage them to implement ->exec_op() instead. Move the ->erase() hook to the nand_legacy struct to make it clear. Signed-off-by:
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Boris Brezillon authored
Those hooks have been overloaded by some drivers for bad reasons: either the driver was not fitting in the NAND framework and should have been an MTD driver (docg4), or it was not properly implementing the OOB read/write request or had a weird layout where BBM are trashed. In any case, we should discourage people from overloading those methods and encourage them to fix their driver instead. Move the ->block_{bad,markbad}() hooks to the nand_legacy struct to make it clear. Signed-off-by: -
Boris Brezillon authored
Those hooks have been replaced by ->exec_op(). Move them to the nand_legacy struct. Signed-off-by:
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Boris Brezillon authored
Those hooks have been replaced by ->exec_op(). Move them to the nand_legacy struct. Signed-off-by:
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Boris Brezillon authored
All those hooks have been replaced by ->exec_op(). Move them to the nand_legacy struct. Signed-off-by:
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Boris Brezillon authored
We regularly have new NAND controller drivers that are making use of fields/hooks that we want to get rid of but can't because of all the legacy drivers that we might break if we do. So, instead of removing those fields/hooks, let's move them to a sub-struct which is clearly documented as deprecated. We start with the ->IO_ADDR_{R,W] fields. Signed-off-by: -
Boris Brezillon authored
There's no point in poisoning the ->IO_ADDR_{R,W}, a NULL pointer is just as good to detect unexpected ->IO_ADDR_{R,W} usage. Signed-off-by: -
Boris Brezillon authored
The only reason we were skipping nand_scan_ident() when maxchips == 0 was to make the docg4 to work. Now that this driver is gone we can remove this special case and return an error when maxchips is 0. Suggested-by:
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Boris Brezillon authored
There's no good reason to make maxchips a signed integer, since only positive values are valid. Make it an unsigned int. Signed-off-by:
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Boris Brezillon authored
The docg4 driver has been removed. Remove the code that was registering a docg4 device. Suggested-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Boris Brezillon authored
The diskonchip G4 driver does not fit very well in the raw/parallel NAND framework simply because such chips have an internal controller translating DoC-specific commands into NAND ones. Keeping such a driver in the raw NAND framework is a real burden for NAND maintainers. Not to mention that some parts of this driver are a bit worrisome: - writes are done by subpages, even though we're interfacing with an MLC chip which are known to not support subpage writes very well (it might be that the FTL handles the complexity for us though) - some part of the code are simply ignoring return codes of function that can fail in a few occasions - there's a hack to support OOB writes when no data is provided. This operation is not supported by the chip and should have been rejected, and nandwrite and other userspace tools should have been patched to deal with such devices - the driver is apparently broken when ignore_badblocks module param is not set to 1 and nobody noticed that (don't know since when this is the case, but it's not a recent change) http://lists.infradead.org/pipermail/linux-mtd/2018-July/082472.html Add to that the fact that we already have a docg3 driver in drivers/mtd/devices/docg3.c and, looking at the code (and regs), it seems docg3 and docg4 have a lot in common (even the author of this driver seemed to have realized that interfacing with the raw NAND framework might have been a bad idea http://lists.infradead.org/pipermail/linux-mtd/2012-January/039517.html). For all these reasons, I'm proposing to remove this driver. If anyone ever wants to add support for this chip back, I'd suggest extending the docg3 driver instead of adding a completely new driver. Signed-off-by:
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Miquel Raynal authored
Add support for the layout used by 2kiB page NAND chips requesting at least 8-bit of correction per 512 bytes. This layout requires a bit of handling as: 1/ It can only fit if the NAND chip has at least 128 OOB bytes. 2/ The Bad Block Markers are located in the middle of the data bytes and shall not be used. 3/ It has been experimentally observed that, for certain layouts, the ECC engine tries to correct data while it should not because the errors are uncorrectable. While this is harmless for truly bad pages, it creates bitflips in empty pages. To avoid such scenario that augments artificially the number of bitflips we re-read in raw mode the entire page instead of just the ECC bytes. This is done only for this layout to avoid an unneeded penalty with other setups. Signed-off-by:
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Miquel Raynal authored
We are about to support a new layout that triggers a faulty mechanism in BCH engine that creates bitflips in erased pages. Before adding the quirk that will workaround this issue, this patch just reworks a bit the section that handles ECC failures in BCH read path. Signed-off-by:
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Boris Brezillon authored
Let's make the raw NAND API consistent by patching all helpers and hooks to take a nand_chip object instead of an mtd_info one or remove the mtd_info object when both are passed. Let's tackle the nand_erase_nand() helper. Signed-off-by:
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