An error occurred fetching the project authors.
  1. 18 May, 2020 1 commit
  2. 30 Apr, 2020 1 commit
  3. 01 Nov, 2019 2 commits
  4. 01 Oct, 2019 1 commit
  5. 23 Aug, 2019 1 commit
  6. 22 Jul, 2019 1 commit
    • Geert Uytterhoeven's avatar
      clk: renesas: cpg-mssr: Fix reset control race condition · e1f1ae80
      Geert Uytterhoeven authored
      The module reset code in the Renesas CPG/MSSR driver uses
      read-modify-write (RMW) operations to write to a Software Reset Register
      (SRCRn), and simple writes to write to a Software Reset Clearing
      Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
      User's Manuals.
      
      However, this may cause a race condition when two devices are reset in
      parallel: if the reset for device A completes in the middle of the RMW
      operation for device B, device A may be reset again, causing subtle
      failures (e.g. i2c timeouts):
      
      	thread A			thread B
      	--------			--------
      
      	val = SRCRn
      	val |= bit A
      	SRCRn = val
      
      	delay
      
      					val = SRCRn (bit A is set)
      
      	SRSTCLRn = bit A
      	(bit A in SRCRn is cleared)
      
      					val |= bit B
      					SRCRn = val (bit A and B are set)
      
      This can be reproduced on e.g. Salvator-XS using:
      
          $ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done &
          $ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done &
      
          i2c-rcar e6510000.i2c: error -110 : 40000002
          i2c-rcar e66d8000.i2c: error -110 : 40000002
      
      According to the R-Car Gen3 Hardware Manual Errata for Rev.
      0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware
      User's Manual, writes to SRCRn do not require read-modify-write cycles.
      
      Note that the R-Car Gen2 Hardware User's Manual has not been updated
      yet, and still says a read-modify-write sequence is required.  According
      to the hardware team, the reset hardware block is the same on both R-Car
      Gen2 and Gen3, though.
      
      Hence fix the issue by replacing the read-modify-write operations on
      SRCRn by simple writes.
      Reported-by: default avatarYao Lihua <Lihua.Yao@desay-svautomotive.com>
      Fixes: 6197aa65 ("clk: renesas: cpg-mssr: Add support for reset control")
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Tested-by: default avatarLinh Phung <linh.phung.jy@renesas.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      e1f1ae80
  7. 20 Jun, 2019 3 commits
  8. 04 Jun, 2019 2 commits
  9. 15 May, 2019 1 commit
    • Stephen Boyd's avatar
      clk: Remove io.h from clk-provider.h · 62e59c4e
      Stephen Boyd authored
      Now that we've gotten rid of clk_readl() we can remove io.h from the
      clk-provider header and push out the io.h include to any code that isn't
      already including the io.h header but using things like readl/writel,
      etc.
      
      Found with this grep:
      
        git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \
        	xargs git grep -l \
      	-e '\<__iowrite32_copy\>' --or \
      	-e '\<__ioread32_copy\>' --or \
      	-e '\<__iowrite64_copy\>' --or \
      	-e '\<ioremap_page_range\>' --or \
      	-e '\<ioremap_huge_init\>' --or \
      	-e '\<arch_ioremap_pud_supported\>' --or \
      	-e '\<arch_ioremap_pmd_supported\>' --or \
      	-e '\<devm_ioport_map\>' --or \
      	-e '\<devm_ioport_unmap\>' --or \
      	-e '\<IOMEM_ERR_PTR\>' --or \
      	-e '\<devm_ioremap\>' --or \
      	-e '\<devm_ioremap_nocache\>' --or \
      	-e '\<devm_ioremap_wc\>' --or \
      	-e '\<devm_iounmap\>' --or \
      	-e '\<devm_ioremap_release\>' --or \
      	-e '\<devm_memremap\>' --or \
      	-e '\<devm_memunmap\>' --or \
      	-e '\<__devm_memremap_pages\>' --or \
      	-e '\<pci_remap_cfgspace\>' --or \
      	-e '\<arch_has_dev_port\>' --or \
      	-e '\<arch_phys_wc_add\>' --or \
      	-e '\<arch_phys_wc_del\>' --or \
      	-e '\<memremap\>' --or \
      	-e '\<memunmap\>' --or \
      	-e '\<arch_io_reserve_memtype_wc\>' --or \
      	-e '\<arch_io_free_memtype_wc\>' --or \
      	-e '\<__io_aw\>' --or \
      	-e '\<__io_pbw\>' --or \
      	-e '\<__io_paw\>' --or \
      	-e '\<__io_pbr\>' --or \
      	-e '\<__io_par\>' --or \
      	-e '\<__raw_readb\>' --or \
      	-e '\<__raw_readw\>' --or \
      	-e '\<__raw_readl\>' --or \
      	-e '\<__raw_readq\>' --or \
      	-e '\<__raw_writeb\>' --or \
      	-e '\<__raw_writew\>' --or \
      	-e '\<__raw_writel\>' --or \
      	-e '\<__raw_writeq\>' --or \
      	-e '\<readb\>' --or \
      	-e '\<readw\>' --or \
      	-e '\<readl\>' --or \
      	-e '\<readq\>' --or \
      	-e '\<writeb\>' --or \
      	-e '\<writew\>' --or \
      	-e '\<writel\>' --or \
      	-e '\<writeq\>' --or \
      	-e '\<readb_relaxed\>' --or \
      	-e '\<readw_relaxed\>' --or \
      	-e '\<readl_relaxed\>' --or \
      	-e '\<readq_relaxed\>' --or \
      	-e '\<writeb_relaxed\>' --or \
      	-e '\<writew_relaxed\>' --or \
      	-e '\<writel_relaxed\>' --or \
      	-e '\<writeq_relaxed\>' --or \
      	-e '\<readsb\>' --or \
      	-e '\<readsw\>' --or \
      	-e '\<readsl\>' --or \
      	-e '\<readsq\>' --or \
      	-e '\<writesb\>' --or \
      	-e '\<writesw\>' --or \
      	-e '\<writesl\>' --or \
      	-e '\<writesq\>' --or \
      	-e '\<inb\>' --or \
      	-e '\<inw\>' --or \
      	-e '\<inl\>' --or \
      	-e '\<outb\>' --or \
      	-e '\<outw\>' --or \
      	-e '\<outl\>' --or \
      	-e '\<inb_p\>' --or \
      	-e '\<inw_p\>' --or \
      	-e '\<inl_p\>' --or \
      	-e '\<outb_p\>' --or \
      	-e '\<outw_p\>' --or \
      	-e '\<outl_p\>' --or \
      	-e '\<insb\>' --or \
      	-e '\<insw\>' --or \
      	-e '\<insl\>' --or \
      	-e '\<outsb\>' --or \
      	-e '\<outsw\>' --or \
      	-e '\<outsl\>' --or \
      	-e '\<insb_p\>' --or \
      	-e '\<insw_p\>' --or \
      	-e '\<insl_p\>' --or \
      	-e '\<outsb_p\>' --or \
      	-e '\<outsw_p\>' --or \
      	-e '\<outsl_p\>' --or \
      	-e '\<ioread8\>' --or \
      	-e '\<ioread16\>' --or \
      	-e '\<ioread32\>' --or \
      	-e '\<ioread64\>' --or \
      	-e '\<iowrite8\>' --or \
      	-e '\<iowrite16\>' --or \
      	-e '\<iowrite32\>' --or \
      	-e '\<iowrite64\>' --or \
      	-e '\<ioread16be\>' --or \
      	-e '\<ioread32be\>' --or \
      	-e '\<ioread64be\>' --or \
      	-e '\<iowrite16be\>' --or \
      	-e '\<iowrite32be\>' --or \
      	-e '\<iowrite64be\>' --or \
      	-e '\<ioread8_rep\>' --or \
      	-e '\<ioread16_rep\>' --or \
      	-e '\<ioread32_rep\>' --or \
      	-e '\<ioread64_rep\>' --or \
      	-e '\<iowrite8_rep\>' --or \
      	-e '\<iowrite16_rep\>' --or \
      	-e '\<iowrite32_rep\>' --or \
      	-e '\<iowrite64_rep\>' --or \
      	-e '\<__io_virt\>' --or \
      	-e '\<pci_iounmap\>' --or \
      	-e '\<virt_to_phys\>' --or \
      	-e '\<phys_to_virt\>' --or \
      	-e '\<ioremap_uc\>' --or \
      	-e '\<ioremap\>' --or \
      	-e '\<__ioremap\>' --or \
      	-e '\<iounmap\>' --or \
      	-e '\<ioremap\>' --or \
      	-e '\<ioremap_nocache\>' --or \
      	-e '\<ioremap_uc\>' --or \
      	-e '\<ioremap_wc\>' --or \
      	-e '\<ioremap_wc\>' --or \
      	-e '\<ioremap_wt\>' --or \
      	-e '\<ioport_map\>' --or \
      	-e '\<ioport_unmap\>' --or \
      	-e '\<ioport_map\>' --or \
      	-e '\<ioport_unmap\>' --or \
      	-e '\<xlate_dev_kmem_ptr\>' --or \
      	-e '\<xlate_dev_mem_ptr\>' --or \
      	-e '\<unxlate_dev_mem_ptr\>' --or \
      	-e '\<virt_to_bus\>' --or \
      	-e '\<bus_to_virt\>' --or \
      	-e '\<memset_io\>' --or \
      	-e '\<memcpy_fromio\>' --or \
      	-e '\<memcpy_toio\>'
      
      I also reordered a couple includes when they weren't alphabetical and
      removed clk.h from kona, replacing it with clk-provider.h because
      that driver doesn't use clk consumer APIs.
      Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Cc: Chen-Yu Tsai <wens@csie.org>
      Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Acked-by: default avatarSekhar Nori <nsekhar@ti.com>
      Cc: Krzysztof Kozlowski <krzk@kernel.org>
      Acked-by: default avatarMark Brown <broonie@kernel.org>
      Cc: Chris Zankel <chris@zankel.net>
      Acked-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      Acked-by: default avatarJohn Crispin <john@phrozen.org>
      Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      62e59c4e
  10. 10 Dec, 2018 1 commit
  11. 26 Sep, 2018 1 commit
  12. 19 Sep, 2018 2 commits
  13. 11 Sep, 2018 1 commit
    • Chris Brandt's avatar
      clk: renesas: cpg-mssr: Add R7S9210 support · fde35c9c
      Chris Brandt authored
      Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
      Standby.
      
      The Module Standby HW in the RZ/A series is very close to R-Car HW, except
      for how the registers are laid out.
      The MSTP registers are only 8-bits wide, there are no status registers
      (MSTPSR), and the register offsets are a little different. Since the RZ/A
      hardware manuals refer to these registers as the Standby Control Registers,
      we'll use that name to distinguish the RZ/A type from the R-Car type.
      Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
      Acked-by: Rob Herring <robh@kernel.org> # DT bits
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      fde35c9c
  14. 31 Aug, 2018 1 commit
  15. 27 Aug, 2018 2 commits
  16. 05 Jun, 2018 1 commit
    • Geert Uytterhoeven's avatar
      clk: renesas: cpg-mssr: Stop using printk format %pCr · ef4b0be6
      Geert Uytterhoeven authored
      Printk format "%pCr" will be removed soon, as clk_get_rate() must not be
      called in atomic context.
      
      Replace it by open-coding the operation.  This is safe here, as the code
      runs in task context.
      
      Link: http://lkml.kernel.org/r/1527845302-12159-2-git-send-email-geert+renesas@glider.be
      To: Jia-Ju Bai <baijiaju1990@gmail.com>
      To: Jonathan Corbet <corbet@lwn.net>
      To: Michael Turquette <mturquette@baylibre.com>
      To: Stephen Boyd <sboyd@kernel.org>
      To: Zhang Rui <rui.zhang@intel.com>
      To: Eduardo Valentin <edubezval@gmail.com>
      To: Eric Anholt <eric@anholt.net>
      To: Stefan Wahren <stefan.wahren@i2se.com>
      To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Sergey Senozhatsky <sergey.senozhatsky.work@gmail.com>
      Cc: Petr Mladek <pmladek@suse.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: linux-doc@vger.kernel.org
      Cc: linux-clk@vger.kernel.org
      Cc: linux-pm@vger.kernel.org
      Cc: linux-serial@vger.kernel.org
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-renesas-soc@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: Geert Uytterhoeven <geert+renesas@glider.be>
      Cc: stable@vger.kernel.org # 4.5+
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarPetr Mladek <pmladek@suse.com>
      ef4b0be6
  17. 09 May, 2018 1 commit
  18. 16 Apr, 2018 1 commit
  19. 21 Mar, 2018 1 commit
  20. 26 Feb, 2018 1 commit
  21. 20 Feb, 2018 1 commit
  22. 14 Dec, 2017 1 commit
  23. 20 Oct, 2017 3 commits
    • Geert Uytterhoeven's avatar
      clk: renesas: div6: Restore clock state during resume · 9f8c71e5
      Geert Uytterhoeven authored
      On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
      clock configuration.  Register an (optional) notifier to restore the
      DIV6 clock state during system resume.
      
      As DIV6 clocks can be picky w.r.t. modifying multiple register fields at
      once, restore is not implemented by blindly restoring the register
      value, but by using the existing cpg_div6_clock_{en,dis}able() helpers.
      
      Note that this does not yet support DIV6 clocks with multiple parents,
      which do not exist on R-Car Gen3 SoCs.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Tested-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
      9f8c71e5
    • Geert Uytterhoeven's avatar
      clk: renesas: cpg-mssr: Add support to restore core clocks during resume · 1f4023cd
      Geert Uytterhoeven authored
      On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly
      losing clock configuration.  Hence add a notifier chain that can be used
      by core clocks to save/restore clock state during system suspend/resume.
      
      The implementation of the actual clock state save/restore operations is
      clock-specific, and to be registered with the notifier chain in the SoC
      or family-specific cpg_mssr_info.cpg_clk_register() callback.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Tested-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
      1f4023cd
    • Geert Uytterhoeven's avatar
      clk: renesas: cpg-mssr: Restore module clocks during resume · 56086910
      Geert Uytterhoeven authored
      During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their
      clock register state is lost.  Note that as the boot loader skips most
      initialization after system resume, clock register state differs from
      the state encountered during normal system boot, too.
      
      Hence after s2ram, some operations may fail because module clocks are
      disabled, while drivers expect them to be still enabled.  E.g. EtherAVB
      fails when Wake-on-LAN has been enabled using "ethtool -s eth0 wol g":
      
          ravb e6800000.ethernet eth0: failed to switch device to config mode
          ravb e6800000.ethernet eth0: device will be stopped after h/w processes are done.
          ravb e6800000.ethernet eth0: failed to switch device to config
          PM: Device e6800000.ethernet failed to resume: error -110
      
      In addition, some module clocks that were disabled by
      clk_disable_unused() may have been re-enabled, wasting power.
      
      To fix this, restore all bits of the SMSTPCR registers that represent
      clocks under control of Linux.
      
      Notes:
        - While this fixes EtherAVB operation after resume from s2ram,
          EtherAVB cannot be used as an actual wake-up source from s2ram, only
          from s2idle, due to PSCI limitations,
        - To avoid overhead on platforms not needing it, the suspend/resume
          code has a build time dependency on sleep and PSCI support, and a
          runtime dependency on PSCI.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Tested-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
      56086910
  24. 19 Sep, 2017 1 commit
  25. 16 Aug, 2017 1 commit
  26. 20 Jun, 2017 1 commit
  27. 24 May, 2017 6 commits