- 03 Oct, 2019 31 commits
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Tianci.Yin authored
Add Navi12 PCI id support. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tao Zhou authored
There are two cases of reserve error should be ignored: 1) a ras bad page has been allocated (used by someone); 2) a ras bad page has been reserved (duplicate error injection for one page); DRM_ERROR is unnecessary for the failure of bad page reserve Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Adam Zerella authored
Some of the documentation formatting could be improved which will resolve some Sphinx amdgpu build warnings e.g WARNING: Unexpected indentation. WARNING: Block quote ends without a blank line; unexpected unindent. WARNING: Inline emphasis start-string without end-string. Signed-off-by:
Adam Zerella <adam.zerella@gmail.com> Signed-off-by:
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Alex Deucher authored
Add new parameters. Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Yong Zhao authored
These were deleted before, but somehow showed up again. Delete them again. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] HDCP is not fully finished, so we need to be able to build and run the driver without it. [How] Add a Kconfig to toggle it Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We don't support HDCP for pre RAVEN asics [How] Check if we are RAVEN+. Use this to attach the content_protection property, this way usermode can't try to enable HDCP on pre DCN asics. Also we need to update the module on hpd so guard it aswell Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to use HW state to set content protection to ENABLED. This way we know that the link is encrypted from the HW side [How] Create a workqueue that queries the HW every ~2seconds, and sets it to ENABLED or DESIRED based on the result from the hardware Signed-off-by:
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Bhawanpreet Lakha authored
[Why] This is needed for DP as DP can send us info using irq. [How] Check if irq bit is set on short pulse and call the function that handles cpirq in amdgpu_dm_hdcp Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to manage the content protection property changes for different usecase, once cp is DESIRED we need to maintain the ENABLED/DESIRED status for different cases. [How] 1. Attach the content_protection property 2. HDCP enable (UNDESIRED -> DESIRED) call into the module with the correct parameters to start hdcp. Set cp to ENABLED 3. HDCP disable (ENABLED -> UNDESIRED) Call the module to disable hdcp. 3. Handle Special cases (Hotplug, S3, headless S3, DPMS) If already ENABLED: set to DESIRED on unplug/suspend/dpms, and disable hdcp Then on plugin/resume/dpms: enable HDCP Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need this to enable HDCP on linux, as we need events to interact with the hdcp module [How] Add work queue to display manager and handle the creation and destruction of the queue Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to read and write specific i2c and dpcd messages. [How] Created static functions for packing the dpcd and i2c messages for hdcp. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to interact with the hdcp module from the DM, the module has to be interacted with in terms of events [How] Create the files needed for linux hdcp. These files manage the events needed for the dm to interact with the hdcp module. We use the kernel work queue to process the events needed for the module Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to update the hdcp display parameter whenever the link is updated, so the next time there is an update to hdcp we have the latest display info [How] Create a callback, and use this anytime there is a change in the link. This will be used later by the dm. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] All the HDCP transactions should be verified using PSP. [How] This patch calls psp with the correct inputs to verify the steps of authentication. Signed-off-by:
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Bhawanpreet Lakha authored
This module manages HDCP for amdgpu driver. The module behaves as a state machine which handles the different authentication states of HDCP The module is divided into 3 major components +--------+ | Hdcp.c | +--------+ Manages the state machine, sends the events to be executed and communicates with the dm +-----------+ |Execution.c| +-----------+ This executes events based on the current state. Also generates execution results as transition inputs +------------+ |Transition.c| +------------+ Decides the next state based on the input and makes requests to hdcp.c to handle. +-------------+ ------> | Execution.c | ------ | +-------------+ | | V +----+ +--------+ +--------------+ | DM | -----> | Hdcp.c | <------------ | Transition.c | +----+ <----- +--------+ +--------------+ v2: Drop unused function definitions Signed-off-by:Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
DTM is the display topology manager. This is needed to communicate with psp about the display configurations. This patch adds -Loading the firmware -The functions and definitions for communication with the firmware v2: Fix formatting Signed-off-by: -
Bhawanpreet Lakha authored
This patch adds -Loading the firmware -The functions and definitions for communication with the firmware v2: Fix formatting Signed-off-by:
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Aric Cyr authored
[Why] There can be some unsynchronized frames when entering/exiting LFC. This may cause tearing or stuttering at such transitions. [How] Add a enter/exit margin to algorithm to smoothly transition into and out of LFC without desynchronizing frames. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Reza Amini <Reza.Amini@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
Detile buffer size affects dcc caps and therefore needs to be corrected for each ip. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Martin Leung authored
tg_inst may be used uninitialized, so initialize it to 0. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Zhan Liu authored
[Why] When more than 2 displays are connected to the graphics card, only the minimum memory clock is needed. However, when more displays are connected, the minimum memory clock is not sufficient enough to support the overwhelming bandwidth. System will hang under this circumstance. Also, the old code didn't address HBM cards, which has 2 pseudo channels. We need to add the HBM part here. [How] When graphics card connects to 2 or more displays, switch to high memory clock. Also, choose memory multiplier based on whether its regular DRAM or HBM. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Martin Leung authored
[why] seamless boot didn't work for non edp's before [how] removed edp-specific code, made dp read uefi-set link settings. Also fixed a hubbub code line to be consistent with usage of function. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] Presently, there is no way for clocks to be lowered, only raised. [HOW] Compare clock status against previous known clock status, and optimize if different. This requires re-ordering the layout of the dc_clocks structure, as the current ordering allows identical clock states to appear different. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] Some ODM-related register settings are inconsistently updated by VBIOS, causing the state in DC to be invalid, which would then end up crashing in certain use-cases (such as disable/enable device). [how] Check the enabled status of the second pipe when determining the number of OPTC sources. If the second pipe is disabled, set the number of sources to 1 regardless of other settings (that may not be updated correctly). Signed-off-by:
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Anthony Koo authored
[Why] A lot of the time, the backlight characteristic curve maps min backlight to a non-zero value. But there are cases where we want the curve to intersect at 0. In this scenario even if OS never asks to set 0% backlight, the ABM reduction can result in backlight being lowered close to 0. This particularly can cause problems in some LED drivers, and in general just looks like backlight is completely off. [How] Add default cap to disallow backlight from dropping below 1% even after ABM reduction is applied. Signed-off-by:
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Wesley Chalmers authored
[WHY] This change was made because DTO programming was double-buffered, which is itself an issue. After deactivating the DTO double buffer, this change becomes unnecessary. Signed-off-by:
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Wesley Chalmers authored
[WHY] When changing DPP global ref clock, DTO adjustments must take effect immediately, or else underflow may occur. It appears the original decision to double-buffer DTO adjustments was made to prevent underflows that occur when raising DPP ref clock (which is not double-buffered), but that same decision causes similar issues when lowering DPP global ref clock. The better solution is to order the adjustments according to whether clocks are being raised or lowered. Signed-off-by:
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- 17 Sep, 2019 9 commits
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Julian Parkin authored
[Why] Separating the hardware initialization from the creation of the dc structures gives greater flexibility to the dm to override options for debugging. [How] Move the hardware initialization call to a new function, dc_hardware_init. No functional change is intended. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by:
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Lewis Huang authored
[Why] I2C write command always send mot = true will cause sink state incorrect. [How] 1. Remove default i2c write mot = true. 2. Deciding mot flag by is_end_of_payload flag. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Martin Tsai authored
[Why] The new implementation changed the behavior to allow process setMode to DAL when DAL returns empty mode query for unplugged display. This will trigger additional disable_link(). When unplug HDMI from MST dock, driver will update stream->signal to "Virtual". disable_link() will call disable_output() if the signal type is not DP and induce other displays on MST dock show black screen. [How] Don't need to process disable_output() if the signal type is virtual. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
dcn20_calculate_dlg_params was incorrectly indexing pipe src and dst structs when extracting global sync params. Signed-off-by:
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Dmytro Laktyushkin authored
Global sync update was missing vtg update resulting in underflow if vstartup decreased a significant amount. Signed-off-by:
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Stylon Wang authored
[Why] Even if YUV420 is available for video mode, YUV444 is still automatically selected. This poses a problem for compliance tests. [How] Add a per-connector debugfs entry "force_yuv420_output" to force selection of YUV420 mode. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Surface dchub/dpp update would not trigger if a stream update was the only cause. This change now allows stream flags to trigger this update. Signed-off-by:
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Wesley Chalmers authored
[WHY] A function to adjust DPP clocks with DTO already exists; function code is identical to the code replaced here Signed-off-by:
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Mikita Lipski authored
[why] The issue is specific for linux, as on timings such as 8K@60 or 4K@144 DSC should be working in combination with ODM Combine in order to ensure that we can run those timings. The validation for those timings was passing, but when pipe split was happening second pipe wasn't being programmed. [how] Rebuild mapped resources if we split stream for ODM. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
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