- 10 Feb, 2016 3 commits
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Stephen Boyd authored
* clk-fixes: clk: versatile: mask VCO bits before writing
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Linus Walleij authored
The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3 ("clk: versatile-icst: convert to use regmap") Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Sylvain Lemieux authored
The following errors are display in the console during the power-on: [ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12 [ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12 There is no need to register clock "0"; the first clock used is 1; Signed-off-by:
Sylvain Lemieux <slemieux@tycoint.com> Acked-by:
Vladimir Zapolskiy <vz@mleia.com> [sboyd@codeaurora.org: s/prepare/register/] Signed-off-by:
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- 09 Feb, 2016 3 commits
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Masahiro Yamada authored
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"), __clk_init_parent() called .get_parent() only for multi-parent clocks. That commit changed the behavior to call .get_parent() if available even for single-parent clocks and root clocks. It turned out a problem because there are some single-parent clocks that implement .get_parent() callback and return non-zero index. The SOCFPGA clock is the case; the commit broke the SOCFPGA boards. To keep the original behavior, invoke .get_parent() only when num_parents is greater than 1. Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()") Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
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Sudip Mukherjee authored
We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by:
Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by:
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Sudip Mukherjee authored
Add a helper function devm_add_action_or_reset() which will internally call devm_add_action(). But if devm_add_action() fails then it will execute the action mentioned and return the error code. Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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- 08 Feb, 2016 6 commits
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Andreas Färber authored
As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869 ("clk: meson: Add support for Meson clock controller") Signed-off-by:
Andreas Färber <afaerber@suse.de> Acked-by:
Carlo Caione <carlo@endlessm.com> Signed-off-by:
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Arnd Bergmann authored
clang found a bug with the __socfpga_pll_init definition: drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and global variables This moves the __init annotation to the right place so the function actually gets discarded. Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Mike Looijmans authored
There are two TI CDCE clock chips in this file. Move them close together so they're easier to find. No functional change, just cosmetic. Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Alphabetize] Signed-off-by:
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Mike Looijmans authored
Simple cosmetic fix. Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
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Stephen Boyd authored
Merge tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull tegra fixes from Thierry Reding: clk: tegra: Fixes for v4.5-rc3 This set contains a bunch of miscellaneous fixes that have accumulated over the past couple of weeks, primarily for the Tegra210 support added in v4.5-rc1. * tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
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- 07 Feb, 2016 3 commits
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Stephen Boyd authored
These functions either never existed or were only used in OF_CLK_DECLARE() macros. Remove the dead prototypes. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: -
Stephen Boyd authored
We don't use CLK_IS_ROOT but in a few places in the common clk framework core. Let's replace those checks with a check for the number of parents a clk has instead of the flag, freeing up one flag for something else. We don't remove the flag yet so that things keep building, but we'll remove it once all drivers have removed their flag usage. Signed-off-by: -
Stephen Boyd authored
clk_get() for DT based clks already returns EPROBE_DEFER when the OF clk provider is not present. So having all this code in the clk provider to return EPROBE_DEFER when the gpio isn't ready yet can be replaced with a platform driver that doesn't add the clk provider until the gpio can be requested. Get rid of the OF_CLK_DECLARE and convert this to a platform driver instead. Tested-by:
Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon@solid-run.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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- 02 Feb, 2016 25 commits
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Insu Yun authored
If clock is already unregistered, it returns with holding lock. It needs to be unlocked. Signed-off-by:
Insu Yun <wuninsu@gmail.com> [sboyd@codeaurora.org: Use goto instead] Signed-off-by:
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Arnd Bergmann authored
The clk-vt8500.c driver would previously enter an endless loop when invalid settings got requested, this was now fixed. However, the driver will now return uninitialized data for a subset of those cases instead, as the gcc correctly warns: clk/clk-vt8500.c: In function 'wm8650_find_pll_bits': clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor2 = best_div2; ^ clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor1 = best_div1; ^ clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized] *multiplier = best_mul; This reworks the error handling in the driver so we now return -EINVAL from clk_round_rate() and clk_set_rate() when we get impossible inputs. Signed-off-by: -
Masahiro Yamada authored
If clk_fetch_parent_index() fails, p_rate is unused. Move the assignment after the error checking. Signed-off-by:
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Masahiro Yamada authored
The clk_core_get_parent_by_index can be used as a helper function to simplify the implementation of clk_fetch_parent_index(). Signed-off-by:
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Masahiro Yamada authored
If parent is given with NULL, clk_fetch_parent_index() could return a positive index value. Currently, parent is checked by the callers of this function, but it would be safer to do it in this function. Signed-off-by:
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Masahiro Yamada authored
This loop can be much simpler. If a new parent is available for orphan clocks, __clk_init_parent(orphan) can detect it. Signed-off-by:
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Masahiro Yamada authored
Currently, clk_register() never checks a circular parent looping, but clock providers could register such an insane clock topology. For example, "clk_a" could have "clk_b" as a parent, and vice versa. In this case, clk_core_reparent() creates a circular parent list and __clk_recalc_accuracies() calls itself recursively forever. The core infrastructure should be kind enough to bail out, showing an appropriate error message in such a case. This helps to easily find a bug in clock providers. (uh, I made such a silly mistake when I was implementing my clock providers first. I was upset because the kernel did not respond, without any error message.) This commit adds a new helper function, __clk_is_ancestor(). It returns true if the second argument is a possible ancestor of the first one. If a clock core is a possible ancestor of itself, it would make a loop when it were registered. That should be detected as an error. Signed-off-by:
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Masahiro Yamada authored
The translation from the index into clk_core is done by clk_core_get_parent_by_index(). The if-block for num_parents == 1 case is duplicating the code in the clk_core_get_parent_by_index(). Drop the "if (num_parents == 1)" from the special case. Instead, set the index to zero if .get_parent() is missing. Signed-off-by:
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Masahiro Yamada authored
The .get_parent is mandatory for multi-parent clocks. Move the check to __clk_core_init(), like other callback checkings. Signed-off-by:
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Jon Hunter authored
Sparse reports the following warnings for structures and functions that should be declared static: drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol 'tegra_super_gen_info_gen4' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol 'tegra_super_gen_info_gen5' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol 'tegra_super_clk_init' was not declared. Should it be static? Fix this by making the above static. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Jon Hunter authored
Sparse reports the following warnings for functions in clk-tegra210.c that should be declared as static: drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol 'tegra210_pllcx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol '_pllc_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol '_pllc2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol '_pllc3_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol '_plla1_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol 'tegra210_plla_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol 'tegra210_plld_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol 'tegra210_plld2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol 'tegra210_plldp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol 'tegra210_pllc4_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol 'tegra210_pllre_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol 'tegra210_pllx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol 'tegra210_pllmb_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol 'tegra210_pllp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol 'tegra210_pllu_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol 'tegra210_clk_adjust_vco_min' was not declared. Should it be static? Fix this by declaring the above as static. Signed-off-by:
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Jon Hunter authored
Sparse generates the following warning for the pll_m params structure: drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry defined twice drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here Fix this by correcting the index for the MISC1 register. Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks") Signed-off-by: -
Jon Hunter authored
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined but not used and when the OVERRIDE bit is cleared in tegra210_pll_init() the code directly uses the bit number. Therefore, use the definition, PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit. Signed-off-by:
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Jon Hunter authored
If the pll_u is not configured by the bootloader, then on kernel boot the following warning is seen: clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out1 ------------[ cut here ]------------ WARNING: at drivers/clk/tegra/clk.c:269 Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1 Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT) task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000 PC is at tegra_init_from_table+0x140/0x164 LR is at tegra_init_from_table+0x140/0x164 pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045 sp : ffffffc0bc0abd50 x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8 x27: ffffffc000a06000 x26: ffffffc0bc019780 x25: ffffffc00086a708 x24: ffffffc00086a790 x23: ffffffc0006d7188 x22: ffffffc0bc010000 x21: 000000000000016e x20: ffffffc0bc00d100 x19: ffffffc000944178 x18: 0000000000000007 x17: 000000000000000e x16: 0000000000000001 x15: 0000000000000007 x14: 000000000000000e x13: 0000000000000013 x12: 000000000000001a x11: 000000000000004d x10: 0000000000000750 x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0 x7 : 0000000000000001 x6 : 0000000002d5f0f8 x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000002 x2 : ffffffc000996724 x1 : 0000000000000000 x0 : 0000000000000032 ---[ end trace cbd20ae519e92ced ]--- Call trace: [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164 [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28 [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24 [<ffffffc00008291c>] do_one_initcall+0x90/0x194 [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8 [<ffffffc000636bb0>] kernel_init+0x10/0xdc [<ffffffc000085cd0>] ret_from_fork+0x10/0x40 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out2 ------------[ cut here ]------------ pll_u can be either controlled by software or hardware and this is selected via the OVERRIDE bit in the pll_u base register. In the function tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects hardware control of the pll. However, at the same time the pll_u clocks are populated in the init_table for tegra210 and so software will try to configure the pll_u if it is not already configured and hence, the above warning is seen when the pll fails to lock. Remove the pll_u clocks from the init_table so that software does not try to configure this pll on boot. Signed-off-by:
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Jon Hunter authored
The EMC clock sources for Tegra210 currently incorrectly include pll_c2 and pll_c3. However, both of these should have been pll_mb as shown in the TRM. If Tegra210 happens to be configured such that the pll_mb is the default clock for the EMC, as configured by the bootloader, then this will cause a system hang on boot. This is because the kernel will disable the pll_mb when disabling unused clock as it appears to be unused when it is not. Also add the additional pll_p clock source for the EMC. Signed-off-by:
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Jon Hunter authored
The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by:
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Amitoj Kaur Chawla authored
for_each_child_of_node() performs an of_node_get() on each iteration, so before breaking out of the loop an of_node_put() is required. Found using Coccinelle. The semantic patch used for this is as follows: // <smpl> @@ expression e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by:Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by:
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Mark Kuo authored
The PLLE SS coefficients are different between Tegra210 and Tegra114. Add SoC generation specific versions for Tegra114 and Tegra210 and use them in their respective ->enable() callbacks. Signed-off-by:
Mark Kuo <mkuo@nvidia.com> Signed-off-by:
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Rhyland Klein authored
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting them. This patch fixes both places where we incorrectly set instead of cleared those bits. Signed-off-by:
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Mark Kuo authored
Software should not disable PLLE if PLLE is already put under hardware control. Signed-off-by:
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Rhyland Klein authored
The logic for calculating the input rate used when figuring out the proper dynamic steps for pllx was incorrect. It is supposed to be calculated using parent_rate / m but it was just using the parent rate directly, therefore using the wrong step values. Signed-off-by:
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Andrew Bresticker authored
Since the ->enable() callback is called with a spinlock held, we cannot call potentially blocking functions such as clk_get_rate() or clk_get_parent(), so use the unlocked versions instead. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as it isn't present upstream] Signed-off-by:
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Rhyland Klein authored
When adding the nvenc clock, it was partially named msenc in the code. Since the msenc clock isn't present in Tegra210 and has been replaced by the nvenc clock, its misleading to see it present. Therefore, properly rename it. Signed-off-by:
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Rhyland Klein authored
Some register for PLLM and PLLMB were named MISC0 but according to the TRM, they have different names. Sync up the names to make it easier to understand which register they are really referring to. Signed-off-by:
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Masahiro Yamada authored
These three cases let clk_register() fail. They should be considered as error messages. Signed-off-by:
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