1. 18 Oct, 2013 1 commit
    • Trent Piepho's avatar
      spi: spi-mxs: Always set LOCK_CS · 58f46e41
      Trent Piepho authored
      There are two bits which control the CS line in the CTRL0 register:
      LOCK_CS and IGNORE_CRC.  The latter would be better named DEASSERT_CS
      in SPI mode.
      
      LOCK_CS keeps CS asserted though the entire transfer.  This should
      always be set.  The DMA code will always set it, explicitly on the
      first segment of the first transfer, and then implicitly on all the
      rest by never clearing the bit from the value read from the ctrl0
      register.
      
      The PIO code will explicitly set it for the first transfer, leave it
      set for intermediate transfers, and then clear it for the final
      transfer.  It should not clear it.
      
      The only reason to not set LOCK_CS would be to attempt an altered
      protocol where CS pulses between each word.  Though don't get your
      hopes up if you want to do this, as the hardware doesn't appear to do
      this in any sane manner.  It appears to be related to the hardware
      FIFO fill level.
      
      The code can be simplified by just setting LOCK_CS once and then not
      needing to deal with it at all in the PIO and DMA transfer functions.
      Signed-off-by: default avatarTrent Piepho <tpiepho@gmail.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Shawn Guo <shawn.guo@linaro.org>
      Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      58f46e41
  2. 13 Oct, 2013 17 commits
  3. 12 Oct, 2013 10 commits
  4. 11 Oct, 2013 12 commits