- 14 Dec, 2017 17 commits
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Yongqiang Sun authored
Work around for a hw bug causing optc underflow if blank data double buffer disable and remove mpcc. Checking optc status after otg unlock, after wait mpcc idle check status again, if optc underflow just happens after wait mpcc idle, clear underflow status and enable blank data double buffer. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andrew Jiang authored
Rather than setting it every time there's a full update with surface count > 0, set it when we need to do plane_atomic_disconnect. Also make sure that we unset the flag in plane_atomic_disable, so that in the event we run through a sequence where we do disconnect followed by an immediate disable, we do not do unnecessarily request a passive flip to do the optimization. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Signed-off-by:
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Yongqiang Sun authored
There is already wait mpcc idle function. It is better to use the same function for all wait mpcc idle. Signed-off-by:
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Eric Bernstein authored
Fix update_mpcc logic to only call assert_mpcc_idle_before_connect if mpcc is not already being used (and required removal). Update set_out_rate_control to include optional flow control parameter. In init_mpcc_from_hw check for case where bot_sel is same as mpcc_id. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Yongqiang Sun authored
Signed-off-by:
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Harry Wentland authored
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_ctx' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_vbios' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_ip' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_soc' Signed-off-by:
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Harry Wentland authored
pipe_ctx->stream and pipe_ctx->plane_state are never NULL Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2111 set_default_colors() error: we previously assumed 'pipe_ctx->stream' could be null (see line 2101) Signed-off-by:
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Harry Wentland authored
plane_res.mi (memory interface) can never be NULL for DCE110 Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2881 dce110_apply_ctx_for_surface() error: we previously assumed 'pipe_ctx->plane_res.mi' could be null (see line 2873) Signed-off-by:
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Harry Wentland authored
NULL check issue found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:1976 dc_link_setup_psr() warn: variable dereferenced before check 'link' (see line 1970) We don't use these functions so might as well remove them. Signed-off-by:
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Eric Bernstein authored
Integrating MPC pseudocode to support new blending cases with secondary MPCC list. This includes a design change to MPC data structures and interfaces. Signed-off-by:
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Tony Cheng authored
Signed-off-by:
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Charlene Liu authored
[Description] in eDP+ HDMI/DP clone or extended configuration, audio inst changed from inst 1 to inst0. No failure related this though, just playback device endpoint inst changed. Also remove one addition register read. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Yongqiang Sun authored
Before power gate plane, mpcc idle wait is processed, no need to wait another time. Signed-off-by:
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Rex Zhu authored
Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Roger He authored
Signed-off-by:
Roger He <Hongbo.He@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 13 Dec, 2017 9 commits
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Rex Zhu authored
RV implementation was missing these callbacks. Used to fetch the clock values for other components. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Alex Deucher authored
No longer used. Reviewed-by:
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Alex Deucher authored
The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by:
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Alex Deucher authored
The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by:
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Alex Deucher authored
Leftover from bring up. Acked-by:
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Alex Deucher authored
The golden register arrays were empty so the function was effectively useless. Acked-by:
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Alex Deucher authored
They are not used any longer. We get the scratch register locations from the vbios directly now. Acked-by:
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Alex Deucher authored
Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by:
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- 12 Dec, 2017 14 commits
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Alex Deucher authored
All functions should have nbio_v* prefix. Acked-by:
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Frank Min authored
this fix the VCE world switch hang issue Signed-off-by:
Frank Min <Frank.Min@amd.com> Acked-by:
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Monk Liu authored
Should be 0. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
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Monk Liu authored
We are polling so no need for INT. Signed-off-by:
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Monk Liu authored
this VRAM evict is not needed and also cost 2seconds to finish because the IRQ is software side disabled before it. Signed-off-by:
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Monk Liu authored
fix calculation. Signed-off-by:
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Monk Liu authored
shrink_pages is in unit of Order after ttm_page_pool_free, but it is used by nr_free in next round so need change it into native page unit Signed-off-by:
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Christian König authored
And also provide the level for which we need a PDE. Signed-off-by:
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Christian König authored
Now instead of one submission for each PDE batch them together over all PDs who need an update. Signed-off-by:
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Christian König authored
No more double house keeping. Signed-off-by:
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Christian König authored
Not needed any more. Signed-off-by:
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Christian König authored
We can do this with a simple mask as well. Signed-off-by:
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Pixel Ding authored
On Tonga VF, there're 2 sources updating wptr registers for sdma3: 1) polling mem and 2) doorbell. When doorbell and polling mem are both enabled on sdma3, there will be collision hit in occasion between those two sources when ucode and h/w are doing the updating on wptr register in parallel. Issue doesn't happen on CP GFX/Compute since CP drops all doorbell writes when VF is inactive. So enable polling mem and don't use doorbell for SDMA3. Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
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Christian König authored
Horrible inefficient, but avoids problems when the root PD size becomes to big. v2: remove incr as well. Signed-off-by:
Chunming Zhou <davdi1.zhou@amd.com> Signed-off-by:
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