- 19 Sep, 2017 30 commits
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Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, but audio is not yet enabled in r8a7792.dtsi, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Biju Das authored
Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Signed-off-by:
Chris Paterson <chris.paterson2@renesas.com> Signed-off-by:
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Wolfram Sang authored
The WP pins are ACTIVE_HIGH, fix it in the DTS. Fixes: 2b41091b ("ARM: dts: alt: add SDHI0 and 1 support") Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Biju Das authored
Signed-off-by:
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Biju Das authored
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by:
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Biju Das authored
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by:
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Biju Das authored
Define the r8a7743 generic part of the USB PHY device node. Signed-off-by:
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Biju Das authored
Add device nodes for the r8a7743 internal PCI bridge devices. Signed-off-by:
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Biju Das authored
Define the iWave RainboW-G22D board dependent part of the Ethernet AVB device node. On some older versions of the platform (before R4.0) the phy address may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will be the first mainstream release), hence using 3 in the dts. Signed-off-by:
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Biju Das authored
Adding pinctrl support for scif4 interface. Signed-off-by:
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Biju Das authored
Define the iWave RainboW-G20D-Qseven board dependent part of the RTC device node. Signed-off-by:
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Biju Das authored
Signed-off-by:
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Biju Das authored
Add Ethernet AVB support for r8a7745 SoC. Signed-off-by:
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Jacopo Mondi authored
Add device nodes for user leds on gr-peach board. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
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Jacopo Mondi authored
Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by:
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Jacopo Mondi authored
Remove an empty line in gr-peach device tree source file. Signed-off-by:
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Geert Uytterhoeven authored
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by:
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Geert Uytterhoeven authored
Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by:
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Fabrizio Castro authored
Add support for the bq32000 RTC to the iwg22m device tree. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by:
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Fabrizio Castro authored
Add eMMC support for iW-RainboW-G22M-SM. Signed-off-by:
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Fabrizio Castro authored
Add MMC interface support for r8a7745 SoC. Signed-off-by:
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Fabrizio Castro authored
Add I2C[0-5] devices to the r8a7745 device tree. Signed-off-by:
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Biju Das authored
Add support for iWave RainboW-G22D-SODIMM board based on RZ/G1E. Signed-off-by:
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Biju Das authored
Add support for iWave RZG1E SODIMM System On Module. http://www.iwavesystems.com/rz-g1e-sodimm-module.htmlSigned-off-by:
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Biju Das authored
Describe GPIO blocks in the R8A7745 device tree. Signed-off-by:
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Biju Das authored
Define the iWave RainboW-G20D-Qseven board dependent part of the SDHI1 device node. Signed-off-by:
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- 18 Sep, 2017 9 commits
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Biju Das authored
Enable the SDHI0 controller on iWave RZG1M Qseven SOM. Signed-off-by:
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Biju Das authored
Add the SDHI controllers to the r8a7743 device tree. Signed-off-by:
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Geert Uytterhoeven authored
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by:
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Geert Uytterhoeven authored
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by:
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Geert Uytterhoeven authored
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by:
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Geert Uytterhoeven authored
Convert the R-Car E2 SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by:
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Geert Uytterhoeven authored
Convert the R-Car M2-N SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by:
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Geert Uytterhoeven authored
Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by:
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Geert Uytterhoeven authored
Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by:
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- 16 Sep, 2017 1 commit
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Linus Torvalds authored
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