1. 09 Jan, 2020 11 commits
  2. 08 Jan, 2020 3 commits
    • José Roberto de Souza's avatar
      drm/i915/display: Fix warning about MST and DDI restrictions · 542dfab5
      José Roberto de Souza authored
      Capturing the restrictions of the BSpec pages bellow:
      
      SKL and CNL do not support MST in DDI E, DDI E only support 2 lanes
      and it is mostly used to support a 4 lanes eDP panel together with
      DDI A.
      ICL's DDI E support MST just like other ports but DDI A is still eDP
      and MIPI only.
      TGL supports MST in any DDI, including DDI A but TGL has it's own
      ddi_pre_enable_dp function already without any warning.
      
      [  215.579791] ------------[ cut here ]------------
      [  215.579794] WARN_ON(is_mst && (port == PORT_A || port == PORT_E))
      [  215.579875] WARNING: CPU: 0 PID: 268 at drivers/gpu/drm/i915/display/intel_ddi.c:3576 intel_ddi_pre_enable+0x124/0xea0 [i915]
      [  215.579878] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 btusb btrtl btbcm btintel bluetooth prime_numbers snd_hda_intel snd_intel_dspcfg snd_hda_codec e1000e snd_hwdep snd_hda_core asix mei_hdcp cdc_ether x86_pkg_temp_thermal mei_me snd_pcm r8152 coretemp usbnet mei crct10dif_pclmul mii ptp ecdh_generic crc32_pclmul i2c_i801 ecc pps_core ghash_clmulni_intel thunderbolt
      [  215.579905] CPU: 0 PID: 268 Comm: kworker/0:2 Tainted: G        W         5.4.0-rc8-zeh+ #1307
      [  215.579907] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3201.A00.1905140358 05/14/2019
      [  215.579912] Workqueue: events_long drm_dp_mst_link_probe_work
      [  215.579975] RIP: 0010:intel_ddi_pre_enable+0x124/0xea0 [i915]
      [  215.579978] Code: ff 8b 7c 24 10 89 44 24 30 85 ff 74 1f f7 44 24 18 fb ff ff ff 75 15 48 c7 c6 98 fa 48 a0 48 c7 c7 d3 df 4a a0 e8 cf d5 d0 e0 <0f> 0b 0f b6 4c 24 2c 41 8b b5 04 06 00 00 4c 89 e7 41 0f b6 95 0c
      [  215.579980] RSP: 0018:ffffc90001a5f990 EFLAGS: 00010286
      [  215.579984] RAX: 0000000000000000 RBX: ffff88848356a000 RCX: 0000000000000000
      [  215.579986] RDX: 0000000000001df1 RSI: ffff88849340c998 RDI: ffffffff821489c5
      [  215.579989] RBP: ffff88848356a000 R08: 00000000c021a419 R09: 0000000000000000
      [  215.579991] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848356a118
      [  215.579994] R13: ffff88847f39c000 R14: ffff88847fe70000 R15: ffff88848356a000
      [  215.579996] FS:  0000000000000000(0000) GS:ffff88849f800000(0000) knlGS:0000000000000000
      [  215.579999] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [  215.580001] CR2: 000055d3d5a26bc0 CR3: 0000000480ba6005 CR4: 0000000000760ef0
      [  215.580004] PKRU: 55555554
      [  215.580006] Call Trace:
      [  215.580014]  ? drm_dp_mst_topology_put_port+0x6f/0x130
      [  215.580072]  intel_mst_pre_enable_dp+0x14b/0x170 [i915]
      [  215.580129]  intel_encoders_pre_enable+0x76/0x90 [i915]
      [  215.580191]  haswell_crtc_enable+0x84/0x880 [i915]
      [  215.580266]  intel_update_crtc+0x1e4/0x200 [i915]
      [  215.580333]  skl_commit_modeset_enables+0x287/0x420 [i915]
      [  215.580405]  intel_atomic_commit_tail+0x332/0x14e0 [i915]
      [  215.580410]  ? queue_work_on+0x41/0x70
      [  215.580489]  intel_atomic_commit+0x31e/0x350 [i915]
      [  215.580500]  drm_client_modeset_commit_atomic+0x18b/0x220
      [  215.580523]  drm_client_modeset_commit_force+0x4d/0x180
      [  215.580531]  drm_fb_helper_restore_fbdev_mode_unlocked+0x46/0xa0
      [  215.580538]  drm_fb_helper_set_par+0x27/0x50
      [  215.580543]  drm_fb_helper_hotplug_event.part.0+0xa7/0xc0
      [  215.580549]  drm_kms_helper_hotplug_event+0x21/0x30
      [  215.580553]  process_one_work+0x25b/0x5b0
      [  215.580566]  worker_thread+0x4b/0x3b0
      [  215.580578]  kthread+0x100/0x140
      [  215.580581]  ? process_one_work+0x5b0/0x5b0
      [  215.580585]  ? kthread_park+0x80/0x80
      [  215.580591]  ret_from_fork+0x24/0x50
      [  215.580603] irq event stamp: 1393930
      [  215.580606] hardirqs last  enabled at (1393929): [<ffffffff8112a013>] vprintk_emit+0x143/0x330
      [  215.580609] hardirqs last disabled at (1393930): [<ffffffff81001cfa>] trace_hardirqs_off_thunk+0x1a/0x20
      [  215.580613] softirqs last  enabled at (1393434): [<ffffffff81c00389>] __do_softirq+0x389/0x47f
      [  215.580618] softirqs last disabled at (1393423): [<ffffffff810b7199>] irq_exit+0xa9/0xc0
      [  215.580621] ---[ end trace afd44ea9caa6373e ]---
      
      BSpec: 4217
      BSpec: 14004
      BSpec: 20584
      BSpec: 50583
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Lucas De Marchi <lucas.demarchi@intel.com>
      Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200107170922.153612-2-jose.souza@intel.com
      542dfab5
    • José Roberto de Souza's avatar
      drm/i915/display/icl+: Do not program clockgating · 10cd283d
      José Roberto de Souza authored
      Talked with HW team and this is a left over, driver should not
      program clockgating, mg or dekel firmware is reponsible for any
      clockgating programing.
      
      Also removing the register and bits definition related to clockgating.
      
      v2:
      Added WARN_ON
      
      v3:
      Only calling icl_phy_set_clock_gating() on intel_ddi_pre_enable_hdmi
      for GEN11
      
      v4:
      ICL should also not program clockgating (thanks Matt for catching
      this)
      
      BSpec issue: 20885
      BSpec: 49292
      BSpec: 21735
      Cc: Lucas De Marchi <lucas.demarchi@intel.com>
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
      Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200107170922.153612-1-jose.souza@intel.com
      10cd283d
    • José Roberto de Souza's avatar
      drm/i915/display: Force the state compute phase once to enable PSR · 60c6a14b
      José Roberto de Souza authored
      Recent improvements in the state tracking in i915 caused PSR to not be
      enabled when reusing firmware/BIOS modeset, this is due to all initial
      commits returning ealier in intel_atomic_check() as needs_modeset()
      is always false.
      
      To fix that here forcing the state compute phase in CRTC that is
      driving the eDP that supports PSR once. Enable or disable PSR do not
      require a fullmodeset, so user will still experience glitch free boot
      process plus the power savings that PSR brings.
      
      It was tried to set mode_changed in intel_initial_commit() but at
      this point the connectors are not registered causing a crash when
      computing encoder state.
      
      v2:
      - removed function return
      - change arguments to match intel_hdcp_atomic_check
      
      v3:
      - replaced drm includes in intel_psr.h by forward declaration(Jani)
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112253
      Reported-by: <s.zharkoff@gmail.com>
      Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
      Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200106152128.195171-1-jose.souza@intel.com
      60c6a14b
  3. 07 Jan, 2020 13 commits
  4. 06 Jan, 2020 8 commits
  5. 05 Jan, 2020 2 commits
  6. 04 Jan, 2020 3 commits