1. 04 Feb, 2019 19 commits
    • Paul Burton's avatar
      MIPS: Loongson32: Remove DMA & NAND devices from ls1b/board.c · 62c2766c
      Paul Burton authored
      Commit 7b3415f5 ("MIPS: Loongson32: Remove unused platform devices")
      removed the definitions of platform devices which have no in tree
      drivers from common Loongson32 code, but missed their removal from
      Loongson 1B board code in arch/mips/loongson32/ls1b/board.c. This causes
      build failures due to the missing declarations of ls1x_dma_pdev,
      ls1x_nand_pdev & their associated *_set_platdata functions.
      
      Remove the dead code from arch/mips/loongson32/ls1b/board.c to fix the
      build.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Fixes: 7b3415f5 ("MIPS: Loongson32: Remove unused platform devices")
      62c2766c
    • Paul Burton's avatar
      MIPS: Loongson32: Fix config brokenness; select SYS_SUPPORTS_32BIT_KERNEL · d6c2fba5
      Paul Burton authored
      Commit a96d68ba ("MIPS: Loongson32: clarify we don't support MIPS16
      and merge configs") attempted to reduce duplication in Kconfig by
      consolidating some selects common to Loongson 1B & 1C CPUs under
      CPU_LOONGSON1. Unfortunately it clearly wasn't tested because by
      removing SYS_SUPPORTS_32BIT_KERNEL it prevented 32BIT from being enabled
      leading to all sorts of strange build errors from a kernel configured to
      build as neither 32 nor 64 bit.
      
      Both loongson1b_defconfig & loongson1c_defconfig failed to build due to
      this problem.
      
      Revert the cleanup portions of commit a96d68ba ("MIPS: Loongson32:
      clarify we don't support MIPS16 and merge configs"), keeping only its
      removal of the selection of SYS_SUPPORTS_MIPS16.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Fixes: a96d68ba ("MIPS: Loongson32: clarify we don't support MIPS16 and merge configs")
      d6c2fba5
    • Paul Burton's avatar
      MIPS: Don't select ARCH_HAS_SYNC_DMA_FOR_CPU when DMA is coherent · 9ae1f262
      Paul Burton authored
      Commit f263f2a2 ("MIPS: Compile post DMA flush only when needed")
      pushed the selection of ARCH_HAS_SYNC_DMA_FOR_CPU down to various
      SYS_HAS_CPU_* Kconfig entries corresponding to CPUs for which
      cpu_needs_post_dma_flush() might return true, but unfortunately missed
      the fact that some of these CPUs can be used in configurations with
      DMA_NONCOHERENT=n. When this is the case the kernel build does not
      include our definition of arch_sync_dma_for_cpu() from
      arch/mips/mm/dma-noncoherent.c and the build fails with a link error.
      
      One example of this problem is ip27_defconfig:
      
        kernel/dma/direct.o: In function `dma_direct_sync_single_for_cpu':
        direct.c:(.text+0x6c): undefined reference to `arch_sync_dma_for_cpu'
        kernel/dma/direct.o: In function `dma_direct_sync_sg_for_cpu':
        direct.c:(.text+0x1f0): undefined reference to `arch_sync_dma_for_cpu'
        kernel/dma/direct.o: In function `dma_direct_alloc':
        direct.c:(.text+0xc20): undefined reference to `arch_dma_alloc'
        kernel/dma/direct.o: In function `dma_direct_free':
        direct.c:(.text+0xc3c): undefined reference to `arch_dma_free'
        make[1]: *** [Makefile:1021: vmlinux] Error 1
        make: *** [Makefile:152: sub-make] Error 2
      
      Fix this by selecting ARCH_HAS_SYNC_DMA_FOR_CPU only when
      DMA_NONCOHERENT is also selected. The SYS_HAS_CPU_BMIPS5000 case is left
      as-is because systems with that CPU always select DMA_NONCOHERENT
      anyway.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Fixes: f263f2a2 ("MIPS: Compile post DMA flush only when needed")
      9ae1f262
    • Paul Burton's avatar
      MIPS: Enable hugepage support for MIPS64r6 · afd375dc
      Paul Burton authored
      Our hugepage support already exists for MIPS64 CPUs, and is already
      enabled for older architecture revisions. There's nothing MIPSr6
      specific involved, and our hugepage support already works fine for
      MIPS64r6 CPUs such as the I6500, so allow it to be selected in Kconfig.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      afd375dc
    • Paul Burton's avatar
      MIPS: Remove open-coded cmpxchg() in set_pte() · 82f4f66d
      Paul Burton authored
      set_pte() contains an open coded version of cmpxchg() - it atomically
      replaces the buddy pte's value if it is currently zero. Simplify the
      code considerably by just using cmpxchg() instead of reinventing it.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      82f4f66d
    • Paul Burton's avatar
      MIPS: MemoryMapID (MMID) Support · c8790d65
      Paul Burton authored
      Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
      Address Space IDs (ASIDs). The major difference between the two is that
      MMIDs are global - ie. an MMID uniquely identifies an address space
      across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
      wherein each address space is allocated a separate ASID for each CPU
      upon which it is used. This global namespace allows a new GINVT
      instruction be used to globally invalidate TLB entries associated with a
      particular MMID across all coherent CPUs in the system, removing the
      need for IPIs to invalidate entries with separate ASIDs on each CPU.
      
      The allocation scheme used here is largely borrowed from arm64 (see
      arch/arm64/mm/context.c). In essence we maintain a bitmap to track
      available MMIDs, and MMIDs in active use at the time of a rollover to a
      new MMID version are preserved in the new version. The allocation scheme
      requires efficient 64 bit atomics in order to perform reasonably, so
      this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
      will only be included in MIPS64 kernels).
      
      The first, and currently only, available CPU with support for MMIDs is
      the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
      our MMIDs to 16 bits wide in order to prevent the bitmap growing to
      absurd sizes if any future CPU does implement 32 bit MMIDs as the
      architecture manuals suggest is recommended.
      
      When MMIDs are in use we also make use of GINVT instruction which is
      available due to the global nature of MMIDs. By executing a sequence of
      GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to
      each remote CPU in many cases. One complication is that GINVT will
      invalidate wired entries (in all cases apart from type 0, which targets
      the entire TLB). In order to avoid GINVT invalidating any wired TLB
      entries we set up, we make sure to create those entries using a reserved
      MMID (0) that we never associate with any address space.
      
      Also of note is that KVM will require further work in order to support
      MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in
      configuring the MMU. That work is not part of this patch, so for now
      when MMIDs are in use KVM is disabled.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      c8790d65
    • Paul Burton's avatar
      MIPS: Add GINVT instruction helpers · 53511389
      Paul Burton authored
      Add a family of ginvt_* functions making it easy to emit a GINVT
      instruction to globally invalidate TLB entries. We make use of the
      _ASM_MACRO infrastructure to support emitting the instructions even if
      the assembler isn't new enough to support them natively.
      
      An associated STYPE_GINV definition & sync_ginv() function are added to
      emit a sync instruction of type 0x14, which operates as a completion
      barrier for these new GINVT (and GINVI) instructions.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      53511389
    • Paul Burton's avatar
      MIPS: mm: Add set_cpu_context() for ASID assignments · 0b317c38
      Paul Burton authored
      When we gain MMID support we'll be storing MMIDs as atomic64_t values
      and accessing them via atomic64_* functions. This necessitates that we
      don't use cpu_context() as the left hand side of an assignment, ie. as a
      modifiable lvalue. In preparation for this introduce a new
      set_cpu_context() function & replace all assignments with cpu_context()
      on their left hand side with an equivalent call to set_cpu_context().
      
      To enforce that cpu_context() should not be used for assignments, we
      rewrite it as a static inline function.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      0b317c38
    • Paul Burton's avatar
      MIPS: mm: Unify ASID version checks · 42d5b846
      Paul Burton authored
      Introduce a new check_mmu_context() function to check an mm's ASID
      version & get a new one if it's outdated, and a
      check_switch_mmu_context() function which additionally sets up the new
      ASID & page directory. Simplify switch_mm() & various
      get_new_mmu_context() callsites in MIPS KVM by making use of the new
      functions, which will help reduce the amount of code that requires
      modification to gain MMID support.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      42d5b846
    • Paul Burton's avatar
      MIPS: mm: Un-inline get_new_mmu_context · 4ebea49c
      Paul Burton authored
      In preparation for adding MMID support to get_new_mmu_context() which
      will increase the size of the function somewhat, move it from
      asm/mmu_context.h into a C file.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      4ebea49c
    • Paul Burton's avatar
      MIPS: mm: Split obj-y to a file per line · 7e8556d0
      Paul Burton authored
      Split always-included objects to one per line in order to make it easier
      to modify the list of included objects.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      7e8556d0
    • Paul Burton's avatar
      MIPS: mm: Remove local_flush_tlb_mm() · 558ec8ad
      Paul Burton authored
      All 3 variants of local_flush_tlb_mm() are now effectively simple calls
      to drop_mmu_context(). Remove them and use drop_mmu_context() directly.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      558ec8ad
    • Paul Burton's avatar
      MIPS: mm: Remove redundant preempt_disable in local_flush_tlb_mm() · f7908a00
      Paul Burton authored
      The r4k variant of local_flush_tlb_mm() wraps its call to
      drop_mmu_context() with a preempt_disable() & preempt_enable() pair, but
      this is redundant since drop_mmu_context() disables interrupts and from
      Documentation/preempt-locking.txt:
      
        Note that you do not need to explicitly prevent preemption if you are
        holding any locks or interrupts are disabled, since preemption is
        implicitly disabled in those cases.
      
      Remove the redundant preempt_disable() & preempt_enable() calls.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      f7908a00
    • Paul Burton's avatar
      MIPS: mm: Move drop_mmu_context() comment into appropriate block · 6067d47e
      Paul Burton authored
      drop_mmu_context() is preceded by a comment indicating what happens if
      the mm provided is currently active on the local CPU. Move that comment
      into the block that executes in this case, adjusting slightly to reflect
      its new location.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      6067d47e
    • Paul Burton's avatar
      MIPS: mm: Consolidate drop_mmu_context() has-ASID checks · c9b2a3dc
      Paul Burton authored
      If an mm does not have an ASID on the local CPU then drop_mmu_context()
      is always redundant, since there's no context to "drop". Various callers
      of drop_mmu_context() check whether the mm has been allocated an ASID
      before making the call. Move that check into drop_mmu_context() and
      remove it from callers to simplify them.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      c9b2a3dc
    • Paul Burton's avatar
      MIPS: mm: Avoid HTW stop/start when dropping an inactive mm · 67741ba3
      Paul Burton authored
      If drop_mmu_context() is called with an mm that is not currently active
      on the local CPU then there's no need for us to stop & start a hardware
      page table walker because it can't be fetching entries for the ASID
      corresponding to the mm we're operating on.
      
      Move the htw_stop() & htw_start() calls into the block which we run only
      if the mm is currently active, in order to avoid the redundant work.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      67741ba3
    • Paul Burton's avatar
      MIPS: mm: Remove redundant get_new_mmu_context() cpu argument · 4739f7dd
      Paul Burton authored
      get_new_mmu_context() accepts a cpu argument, but implicitly assumes
      that this is always equal to smp_processor_id() by operating on the
      local CPU's TLB & icache.
      
      Remove the cpu argument and have get_new_mmu_context() call
      smp_processor_id() instead.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      4739f7dd
    • Paul Burton's avatar
      MIPS: mm: Remove redundant drop_mmu_context() cpu argument · 9a27324f
      Paul Burton authored
      The drop_mmu_context() function accepts a cpu argument, but it
      implicitly expects that this is always equal to smp_processor_id() by
      allocating & configuring an ASID on the local CPU when the mm is active
      on the CPU indicated by the cpu argument.
      
      All callers do provide the value of smp_processor_id() to the cpu
      argument.
      
      Remove the redundant argument and have drop_mmu_context() call
      smp_processor_id() itself, making it clearer that the cpu variable
      always represents the local CPU.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      9a27324f
    • Paul Burton's avatar
      MIPS: mm: Define activate_mm() using switch_mm() · c653bd04
      Paul Burton authored
      MIPS has separate definitions of activate_mm() & switch_mm() which are
      identical apart from switch_mm() checking that the ASID is valid before
      acquiring a new one.
      
      We know that when activate_mm() is called cpu_context(X, mm) will be
      zero, and this will never be considered a valid ASID because we never
      allow the ASID version number to be zero, instead beginning with version
      1 using asid_first_version(). Therefore switch_mm() will always allocate
      a new ASID when called for a new task, meaning that it will behave
      identically to activate_mm().
      
      Take advantage of this to remove the duplication & define activate_mm()
      using switch_mm() just like many other architectures do.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      c653bd04
  2. 28 Jan, 2019 2 commits
  3. 23 Jan, 2019 3 commits
    • Masahiro Yamada's avatar
      MIPS: remove meaningless generic-(CONFIG_GENERIC_CSUM) += checksum.h · a0f0b69f
      Masahiro Yamada authored
      This line is weird in multiple ways.
      
      (CONFIG_GENERIC_CSUM) might be a typo of $(CONFIG_GENERIC_CSUM).
      
      Even if you add '$' to it, $(CONFIG_GENERIC_CSUM) is never evaluated
      to 'y' because scripts/Makefile.asm-generic does not include
      include/config/auto.conf. So, the asm-generic wrapper of checksum.h
      is never generated.
      
      Even if you manage to generate it, it is never included by anyone
      because MIPS has the checkin header with the same file name:
      
        arch/mips/include/asm/checksum.h
      
      As you see in the top Makefile, the checkin headers are included before
      generated ones.
      
        LINUXINCLUDE    := \
                        -I$(srctree)/arch/$(SRCARCH)/include \
                        -I$(objtree)/arch/$(SRCARCH)/include/generated \
                        ...
      
      Commit 4e0748f5 ("MIPS: Use generic checksum functions for MIPS R6")
      already added the asm-generic fallback code in the checkin header:
      
        #ifdef CONFIG_GENERIC_CSUM
        #include <asm/generic/checksum.h>
        #else
          ...
        #endif
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-kernel@vger.kernel.org
      a0f0b69f
    • Jiaxun Yang's avatar
      MIPS: Loongson32: Revert ISA level to MIPS32R2 · 7e280f6b
      Jiaxun Yang authored
      GS232 core have implemented all necessary mips32r2 instructions.
      Serval missing FP instructions can be emulated by kernel.
      
      The issue of di instruction have been solved.
      Thus we revert the ISA level back to MIPS32R2.
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: keguang.zhang@gmail.com
      7e280f6b
    • Jiaxun Yang's avatar
      MIPS: Loongson32: workaround di issue · bdea8bb1
      Jiaxun Yang authored
      GS232 core used in Loongson-1 processors has a bug that
      di instruction doesn't save the irqflag immediately.
      
      Workaround by set irqflag in CP0 before di instructions
      as same as Loongson-3.
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: keguang.zhang@gmail.com
      bdea8bb1
  4. 22 Jan, 2019 16 commits