- 07 Mar, 2018 15 commits
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Shirish S authored
In dce110, the plane configuration is such that plane 0 or the primary plane should be rendered with only RGB data. This patch adds the validation to ensure that no video data is rendered on plane 0. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Emily Deng authored
The sdma wptr polling memory is not fast enough, then the sdma wptr register will be random, and not equal to sdma rptr, which will cause sdma engine hang when load driver, so clean up the sdma wptr directly to fix this issue. v2:add comment above the code and correct coding style Reviewed-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Tom St Denis authored
These are required by umr to properly parse bitfield offsets. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexdeucher@amd.com> Signed-off-by:
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Monk Liu authored
to catch error that may schedule in atomic context early on Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Christian König authored
Disable the workaround on imported BOs as well. Signed-off-by:
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Christian König authored
We can use ttm->bdev instead. Signed-off-by:
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Christian König authored
Allow evicting all BOs from the GTT domain. Signed-off-by:
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Rex Zhu authored
Fix compiling error when CONFIG_ACPI not enabled. Change-Id: I5f901adbc799c10b30e5ea79f8f44760e749fae1 Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com>
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Christian König authored
For amdgpu_bo_create_kernel to work the handle must be NULL initialized, otherwise we only try to pin and map the BO. Signed-off-by:
Rex Zhu <rezhu@amd.com> Signed-off-by:
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Rex Zhu authored
replace smu_upper_32_bits/smu_lower_32_bits with the standard kernel macros Reviewed-by:
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Rex Zhu authored
delete those cgs interfaces: amdgpu_cgs_alloc_gpu_mem amdgpu_cgs_free_gpu_mem amdgpu_cgs_gmap_gpu_mem amdgpu_cgs_gunmap_gpu_mem amdgpu_cgs_kmap_gpu_mem amdgpu_cgs_kunmap_gpu_mem Reviewed-by:
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Rex Zhu authored
use amdgpu_bo_create/free_kernel instand. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
This reverts commit e429ea87b2939c4cce1b439baf6d76535a0767f2. Implement Workload Aware Dynamic power management instand of AutoWattman feature in linux. Reviewed-by:
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Rex Zhu authored
Add power profiling mode dynamic switch based on the workloads. Currently, support Cumpute, VR, Video, 3D,power saving with Cumpute have highest prority, power saving have lowest prority. in manual dpm mode, driver will stop auto switch, just save the client's requests. user can set power profiling mode through sysfs. when exit manual dpm mode, driver will response the client's requests. switch based on the client's prority. v2: squash in fixes from Rex Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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- 06 Mar, 2018 6 commits
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Rex Zhu authored
The gfx/compute profiling mode switch is only for internally test. Not a complete solution and unexpectly upstream. so revert it. Reviewed-by:
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Rex Zhu authored
Compute workload tends to be "bursty", Only tune the behavior of nature dpm don't work well for most of such workloads. From test results, Fix sclk in highest two levels can get better performance. so add min sclk setting into the default cumpute workload policy on smu7. user still can change sclk range through sysfs pp_dpm_sclk for better perf/watt. Reviewed-by:
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Rex Zhu authored
It show what parameters can be configured to tune the behavior of natural dpm for perf/watt on smu7. user can select the mode per workload, but even the default per workload settings are not bulletproof. user can configure custom settings per different use case for better perf or better perf/watt. cat pp_power_profile_mode NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL 0 3D_FULL_SCREEN: 0 100 30 0 100 10 1 POWER_SAVING: 10 0 30 - - - 2 VIDEO: - - - 10 16 31 3 VR: 0 11 50 0 100 10 4 COMPUTE: 0 5 30 - - - 5 CUSTOM: 0 0 0 0 0 0 * CURRENT: 0 100 30 0 100 10 Under manual dpm level, user can echo "0/1/2/3/4">pp_power_profile_mode to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE mode. echo "5 * * * * * * * *">pp_power_profile_mode to set custom settings. "5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL" if the parameter enable_sclk/enable_mclk is true, driver will update the following parameters to dpm table. if false, ignore the following parameters. Reviewed-by:
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Rex Zhu authored
use SW method to update DPM settings by updating SRAM directly on CI. Reviewed-by:
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Rex Zhu authored
use SW method to update DPM settings by updating SRAM directly on Tonga. Reviewed-by:
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Rex Zhu authored
use SW method to update DPM settings by updating SRAM directly on Fiji. Reviewed-by:
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- 05 Mar, 2018 19 commits
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Alex Deucher authored
Always set the graphics values to the max for the asic type. E.g., some 1 RB chips are actually 1 RB chips, others are actually harvested 2 RB chips. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353Reviewed-by:
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Alex Deucher authored
Always set the graphics values to the max for the asic type. E.g., some 1 RB chips are actually 1 RB chips, others are actually harvested 2 RB chips. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353Reviewed-by:
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Rex Zhu authored
v2: lock dpm level when update pptable by SW method use SW method to update DPM settings by updating SRAM directly on Polaris. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
it is used for adjust part of dpm settigs per workloads to change the natural dpm behavior for better perf or perf/watt. Reviewed-by:
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Rex Zhu authored
This features controls vega peak current protection to allow for a wider compatibility with power supplies. Reviewed-by:
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Rex Zhu authored
used to set PccThrottleLevel and PccResidencyThreshold Reviewed-by:
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Rex Zhu authored
Get gpu info through adev directly in powerplay Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
it is required if a platform supports PCIe root complex core voltage reduction. After receiving this notification, SBIOS can apply default PCIe root complex power policy. Reviewed-by:
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Rex Zhu authored
Include adev in powerplay instance. so can visit adev directly instand of through cgs interface. Reviewed-by:
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Rex Zhu authored
use adev as input parameter to create powerplay instance directly. delete cgs wrap layer for power play create. Reviewed-by:
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Rex Zhu authored
avoid build error: drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smu9_driver_if.h:342:3: error: redeclaration of enumerator ‘WM_COUNT’ WM_COUNT, ^ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:32:0, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:35, from drivers/gpu/drm/amd/amdgpu/../display/modules/inc/mod_freesync.h:57, from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:48, from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:55, from drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amd_powerplay.h:33, from drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smumgr.h:26, from drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vega10_smumgr.c:24: drivers/gpu/drm/amd/amdgpu/../display/dc/dm_pp_smu.h:43:2: note: previous definition of ‘WM_COUNT’ was here WM_COUNT, Reviewed-by:Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Shirish S authored
The below commit "drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2" introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it. This change leads to BUG hit while performing atomic commit on amd driver. As a fix this patch ensures that we disable the CRTC's with NULL FB by returning -EINVAL and hence triggering fall back to the old behavior and turning off the crtc in atomic_remove_fb(). V2: Added error check for plane_state and removed sanity check for crtc. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Rex Zhu authored
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Michel Dänzer authored
For consistency with other DCE generations. HPD IRQs appear to be working fine. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
The ring status can change during GPU reset, but we still need to be able to schedule TTM buffer moves in the meantime. Otherwise we can ran into problems because of aborted move/fill operations during GPU resets. v2: still check if ring is available during direct submit. Signed-off-by:
Chunming zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
When we reset the GPU we also disable/enable the SDMA, but we don't want to change TTM idea of the VRAM size in the middle of that. Signed-off-by:
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