- 24 May, 2018 14 commits
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Ludovic Barre authored
This patch adds support of external interrupt for gpio[a..k], gpioz Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com>
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Ludovic Barre authored
This patch adds external interrupt (exti) support on stm32mp157c SoC. Signed-off-by:
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Ludovic Barre authored
-Parent domain of stm32gpio evolves to hierarchy domain and could have a handle_fasteoi_irq. So an irq_eoi parent callback is needed for children. -Replace space by tabulation. Signed-off-by:
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Ludovic Barre authored
This patch adds suspend/resume feature for exti hierarchy domain. -suspend function sets wake_active into imr of each banks -resume function restores the mask_cache interrupt into imr of each banks Signed-off-by:
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Ludovic Barre authored
Exti controller has been differently integrated on stm32mp1 SoC. A parent irq has only one external interrupt. A hierachy domain could be used. Handlers are call by parent, each parent interrupt could be masked and unmasked according to the needs. Signed-off-by:
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Ludovic Barre authored
This patch prepares functions which could be reused by next variant of stm32 exti controller. Signed-off-by:
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Ludovic Barre authored
This patch adds host and driver data structures to support different stm32 exti controllers with variants. Signed-off-by:
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Ludovic Barre authored
This patch adds suspend feature. -Use default irq_set_wake function to store wakeup request. -Suspend function set wake_active into imr of each bank and save rising/falling trigger registers. -Resume function restore the mask_cache interrupt into imr of each bank and restore rising/falling trigger registers. Signed-off-by:
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Ludovic Barre authored
This patch adds support of rising/falling pending registers. Falling pending register (fpr) is needed for next revision. Signed-off-by:
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Ludovic Barre authored
-WARNING: struct irq_domain_ops should normally be const -CHECK: Alignment should match open parenthesis Signed-off-by:
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Radoslaw Pietrzyk authored
- In stm32_exti_alloc function, discards irq_domain_set_info with handle_simple_irq. This overwrite the setting defined while init of generic chips. Exti controller manages edge irq type. - Removes acking in chained irq handler as this is done by irq_chip itself inside handle_edge_irq - removes unneeded irq_domain_ops.xlate callback Acked-by:
Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Signed-off-by:
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Yixun Lan authored
The Meson-AXG SoC uses the same GPIO interrupt controller IP block as the other Meson SoCs. A total of 100 pins can be spied on, which is the sum of: - 255:100 Undefined(no interrupt) - 99:84, 16 pins on bank GPIOY - 83:61, 23 pins on bank GPIOX - 60:40, 21 pins on bank GPIOA - 39:25, 15 pins on bank BOOT - 24:14, 11 pins on bank GPIOZ - 13:0 , 14 pins in the AO domain Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
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Yixun Lan authored
Update the dt-binding documentation to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-AXG SoC. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Yixun Lan authored
The double quotes seems not ASCII type, fix it here. Reviewed-by:
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- 14 May, 2018 12 commits
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Frederic Weisbecker authored
s390 is now the last architecture that entirely overwrites local_softirq_pending() and uses the according default definitions of set_softirq_pending() and or_softirq_pending(). Just move these to s390 to debloat the generic code complexity. Suggested-by:
Peter Zijlstra <peterz@infradead.org> Signed-off-by:
Frederic Weisbecker <frederic@kernel.org> Acked-by:
Thomas Gleixner <tglx@linutronix.de> Acked-by:
Ingo Molnar <mingo@kernel.org>
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Frederic Weisbecker authored
Remove the ad-hoc implementation, the generic code now allows us not to reinvent the wheel. Signed-off-by:
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Frederic Weisbecker authored
Benefit from the generic softirq mask implementation that rely on per-CPU mutators instead of working with raw operators on top of this_cpu_ptr(). Signed-off-by:
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Frederic Weisbecker authored
Remove the ad-hoc implementation, the generic code now allows us not to reinvent the wheel. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David S. Miller <davem@davemloft.net> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: James E.J. Bottomley <jejb@parisc-linux.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Rich Felker <dalias@libc.org> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/1525786706-22846-9-git-send-email-frederic@kernel.orgSigned-off-by:
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Frederic Weisbecker authored
Remove the ad-hoc implementation, the generic code now allows us not to reinvent the wheel. Signed-off-by:
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Frederic Weisbecker authored
Benefit from the generic softirq mask implementation that rely on per-CPU mutators instead of working with raw operators on top of this_cpu_ptr(). Signed-off-by:
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Frederic Weisbecker authored
Consolidate and optimize default softirq mask API implementations. Per-CPU operations are expected to be faster and a few architectures already rely on them to implement local_softirq_pending() and related accessors/mutators. Those will be migrated to the new generic code. Signed-off-by:
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Frederic Weisbecker authored
In order to optimize and consolidate softirq mask accesses, let's convert the default irq_cpustat_t implementation to per-CPU standard API. Signed-off-by:
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Frederic Weisbecker authored
Use nmi_count() instead of accessing directly the irq_stat structure. Its implementation is going to change to use per-CPU, so defer the guts to standard API instead. Signed-off-by:
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Frederic Weisbecker authored
In order to consolidate and optimize generic softirq mask accesses, we first need to convert architectures to use per-cpu operations when possible. Signed-off-by:
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Frederic Weisbecker authored
In order to consolidate and optimize generic softirq mask accesses, we first need to convert architectures to use per-cpu operations when possible. Signed-off-by:
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Ingo Molnar authored
Signed-off-by:
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- 13 May, 2018 14 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86/pti updates from Thomas Gleixner: "A mixed bag of fixes and updates for the ghosts which are hunting us. The scheduler fixes have been pulled into that branch to avoid conflicts. - A set of fixes to address a khread_parkme() race which caused lost wakeups and loss of state. - A deadlock fix for stop_machine() solved by moving the wakeups outside of the stopper_lock held region. - A set of Spectre V1 array access restrictions. The possible problematic spots were discuvered by Dan Carpenters new checks in smatch. - Removal of an unused file which was forgotten when the rest of that functionality was removed" * 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/vdso: Remove unused file perf/x86/cstate: Fix possible Spectre-v1 indexing for pkg_msr perf/x86/msr: Fix possible Spectre-v1 indexing in the MSR driver perf/x86: Fix possible Spectre-v1 indexing for x86_pmu::event_map() perf/x86: Fix possible Spectre-v1 indexing for hw_perf_event cache_* perf/core: Fix possible Spectre-v1 indexing for ->aux_pages[] sched/autogroup: Fix possible Spectre-v1 indexing for sched_prio_to_weight[] sched/core: Fix possible Spectre-v1 indexing for sched_prio_to_weight[] sched/core: Introduce set_special_state() kthread, sched/wait: Fix kthread_parkme() completion issue kthread, sched/wait: Fix kthread_parkme() wait-loop sched/fair: Fix the update of blocked load when newly idle stop_machine, sched: Fix migrate_swap() vs. active_balance() deadlock -
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull scheduler fix from Thomas Gleixner: "Revert the new NUMA aware placement approach which turned out to create more problems than it solved" * 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "sched/numa: Delay retrying placement for automatic NUMA balance after wake_affine()"
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull perf tooling fixes from Thomas Gleixner: "Another small set of perf tooling fixes and updates: - Revert "perf pmu: Fix pmu events parsing rule", as it broke Intel PT event description parsing (Arnaldo Carvalho de Melo) - Sync x86's cpufeatures.h and kvm UAPI headers with the kernel sources, suppressing the ABI drift warnings (Arnaldo Carvalho de Melo) - Remove duplicated entry for westmereep-dp in Intel's mapfile.csv (William Cohen) - Fix typo in 'perf bench numa' options description (Yisheng Xie)" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "perf pmu: Fix pmu events parsing rule" tools headers kvm: Sync ARM UAPI headers with the kernel sources tools headers kvm: Sync uapi/linux/kvm.h with the kernel sources tools headers: Sync x86 cpufeatures.h with the kernel sources perf vendor events intel: Remove duplicated entry for westmereep-dp in mapfile.csv perf bench numa: Fix typo in options -
git://git.infradead.org/users/hch/dma-mappingLinus Torvalds authored
Pull dma-mapping fix from Christoph Hellwig: "Just one little fix from Jean to avoid a harmless but very annoying warning, especially for the drm code" * tag 'dma-mapping-4.17-5' of git://git.infradead.org/users/hch/dma-mapping: swiotlb: silent unwanted warning "buffer is full"
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Marc Zyngier authored
Add the required properties to support the MBI feature on GICv3. Signed-off-by:
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Marc Zyngier authored
You would hope that if you have a GICv3 in your system, you'd use the ITS, as it provides a large interrupt ID space and device isolation. Sadly, some SoC integrations are less than perfect, and the ITS is not usesable on those. The only solution for these systems is to use the MBI interface, and rely on a very small number of possible vectors. This patch thus adds minimal support for PCI/MSI on top of the GICv3 MBI driver. Please don't use it if you can avoid it. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20180508121438.11301-9-marc.zyngier@arm.com
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Marc Zyngier authored
GICv3 offers the possibility to signal SPIs using a pair of doorbells (SETPI, CLRSPI) under the name of Message Based Interrupts (MBI). They can be used as either traditional (edge) MSIs, or the more exotic level-triggered flavour. Let's implement support for platform MSI, which is the original intent for this feature. Signed-off-by:
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Marc Zyngier authored
As we're about to introduce MSI domains based on top of the GICv3 domain, we must make sure nothing the new domains do not alias with the core domain. So let's tag that core domain with the DOMAIN_BUS_WIRED attribute, ensuring it gets picked up by other drivers that use irq_find_host(). Signed-off-by:
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Marc Zyngier authored
At the beginning of times, irq_find_host() was simple. Each device node implemented at most one irq domain, and we were happy. Over time, things have become more complex, and we now have nodes implementing a plurality of domains, tagged by "bus_token". Crutially, users of irq_find_host() all expect the most basic domain to be returned, and not any other domain such as a bus-specific MSI domain. So let's change irq_find_host() to first look for a DOMAIN_BUS_WIRED domain, and only if this fails fallback to DOMAIN_BUS_ANY. Note that this is consistent with what irq_create_fwspec_mapping is already doing, see 530cbe10 ("irqdomain: Allow domain lookup with DOMAIN_BUS_WIRED token"). Signed-off-by:
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Marc Zyngier authored
Inclusion of include/dma-iommu.h when CONFIG_IOMMU_DMA is not selected results in the following splat: In file included from drivers/irqchip/irq-gic-v3-mbi.c:20:0: ./include/linux/dma-iommu.h:95:69: error: unknown type name ‘dma_addr_t’ static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) ^~~~~~~~~~ ./include/linux/dma-iommu.h:108:74: warning: ‘struct list_head’ declared inside parameter list will not be visible outside of this definition or declaration static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) ^~~~~~~~~ scripts/Makefile.build:312: recipe for target 'drivers/irqchip/irq-gic-v3-mbi.o' failed Fix it by including linux/types.h. Signed-off-by: -
Marc Zyngier authored
The ICU and GICP drivers are using an ugly side-band mechanism to find out about the "clear" doorbell when using level interrupts. Let's convert it to level-triggered MSIs, which result in a nice cleanup. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Cc: Rob Herring <robh@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Link: https://lkml.kernel.org/r/20180508121438.11301-4-marc.zyngier@arm.com
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Marc Zyngier authored
Nobody would be insane enough to try and use level triggered MSIs on PCI, but let's make sure it doesn't happen. Also, let's mandate that the irqchip backing the platform MSI domain is providing the IRQCHIP_SUPPORTS_LEVEL_MSI flag. Signed-off-by:
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Marc Zyngier authored
So far, MSIs have been used to signal edge-triggered interrupts, as a write is a good model for an edge (you can't "unwrite" something). On the other hand, routing zillions of wires in an SoC because you need level interrupts is a bit extreme. People have come up with a variety of schemes to support this, which involves sending two messages: one to signal the interrupt, and one to clear it. Since the kernel cannot represent this, we've ended up with side-band mechanisms that are pretty awful. Instead, let's acknoledge the requirement, and ensure that, under the right circumstances, the irq_compose_msg and irq_write_msg can take as a parameter an array of two messages instead of a pointer to a single one. We also add some checking that the compose method only clobbers the second message if the MSI domain has been created with the MSI_FLAG_LEVEL_CAPABLE flags. Signed-off-by:
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