- 07 Jul, 2016 40 commits
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Tom St Denis authored
According to the bringup code ST/CZ share the RLC ENTER/EXIT logic. Tested on my ST board. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Nicolai Hähnle authored
They allow disabling clock and power gating from the kernel command line, which hopefully helps with diagnosing problems in the field. Reviewed-by:
Nicolai Hähnle <Nicolai.Haehnle@amd.com> Signed-off-by:
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Tom St Denis authored
Add tracepoints to the MMIO read/write so we can log MMIO traffic. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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yanyang1 authored
The non-powerplay code handles this directly. Do it in cgs for powerplay. Signed-off-by:
yanyang1 <Young.Yang@amd.com> Reviewed-by: Rex Zhu Rex.Zhu@amd.com Signed-off-by:
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Alex Deucher authored
Was missing the calls to fini. Signed-off-by: -
Alex Deucher authored
Until Dave's patch to support the new hybrid gfx ACPI method goes upstream, we can fallback to the old ATPX method which seems to still work. Signed-off-by: -
Alex Deucher authored
Until Dave's patch to support the new hybrid gfx ACPI method goes upstream, we can fallback to the old ATPX method which seems to still work. Signed-off-by: -
Chunming Zhou authored
so that we could actually reset the GPU when it hangs. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Monk Liu authored
debugfs file added but not released after driver unloaded Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Tom St Denis authored
If a user tries to read a non-multiple of 4 bytes it would have read until the end of the ring potentially crashing the user task. Signed-off-by:
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Tom St Denis authored
They now emit ring data in binary which will be read/written by the userspace tool umr shortly. Signed-off-by:
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Alex Deucher authored
The ATPX power control method does this for you. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Alex Deucher authored
The platform d3 cold is used to power down the dGPU. Reviewed-by:
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Alex Deucher authored
hybrid graphics in this case refers to systems which use the new platform d3 cold ACPI methods as opposed to ATPX for dGPU power control. Reviewed-by:
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Alex Deucher authored
The ATPX power control method does this for you. Reviewed-by:
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Alex Deucher authored
The platform d3 cold is used to power down the dGPU. Reviewed-by:
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Alex Deucher authored
hybrid graphics in this case refers to systems which use the new platform d3 cold ACPI methods as opposed to ATPX for dGPU power control. Reviewed-by:
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Alex Deucher authored
Now that we handle this correctly, there is no need to force it. Reviewed-by:
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Alex Deucher authored
On PX systems without dGPU power control, use PCI_D3hot. Reviewed-by:
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Alex Deucher authored
The runtime pm sequence is different depending on whether or not the platform supports ATPX dGPU power control. Reviewed-by:
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Alex Deucher authored
ATPX dGPU power control requires a 200ms delay between power off and on. This should fix dGPU failures on resume from power off. Reviewed-by:
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Alex Deucher authored
The presence of the power control method should be determined via the presence of the method in function 0. However, some sbioses only set the appropriate bits in function 1 so use then to override a missing power control function. Reviewed-by:
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Alex Deucher authored
Windows 10 (and some 8.1) systems use standardized ACPI calls for hybrid laptops to control dGPU power. Detect those cases and disable the AMD specific ATPX power control. Reviewed-by:
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Alex Deucher authored
Now that we handle this correctly, there is no need to force it. Reviewed-by:
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Alex Deucher authored
On PX systems without dGPU power control, use PCI_D3hot. Reviewed-by:
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Alex Deucher authored
The runtime pm sequence is different depending on whether or not the platform supports ATPX dGPU power control. Reviewed-by:
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Alex Deucher authored
ATPX dGPU power control requires a 200ms delay between power off and on. This should fix dGPU failures on resume from power off. Reviewed-by:
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Alex Deucher authored
The presence of the power control method should be determined via the presence of the method in function 0. However, some sbioses only set the appropriate bits in function 1 so use then to override a missing power control function. Reviewed-by:
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Alex Deucher authored
Windows 10 (and some 8.1) systems use standardized ACPI calls for hybrid laptops to control dGPU power. Detect those cases and disable the AMD specific ATPX power control. Reviewed-by:
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Edmondo Tommasina authored
Reviewed-by:
Edmondo Tommasina <edmondo.tommasina@gmail.com> Signed-off-by:
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Tom St Denis authored
Must wait for SERDES idle before exiting RLC SAFEMODE Signed-off-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
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Eric Huang authored
The maximum OD percentage is 20. Reviewed-by:
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Eric Huang authored
This implements mclk OverDrive(OD) through sysfs. The new entry pp_mclk_od is read/write. The value of input/output is an integer of the overclocking percentage. Reviewed-by:
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Huang Rui authored
This patch makes powercontainment feature configurable. Currently, the powercontainment is not very stable, so add a module parameter to enable/disable it via user mode. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Christian König authored
Remove the job reference counting and just properly destroy it from a work item which blocks on any potential running timeout handler. Signed-off-by:
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Christian König authored
Otherwise the locking becomes rather confusing. Signed-off-by:
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Christian König authored
The driver shouldn't mess with the scheduler internals. Signed-off-by:
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