- 06 Aug, 2010 21 commits
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Sascha Hauer authored
Nand devices with at least 26 bytes of oob data per 512 byte block can have 8bit ecc on v2 type controllers. This is currently not tested, but at least this patch puts the ECC_MODE bit into a well defined state. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
David Woodhouse <David.Woodhouse@intel.com>
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Sascha Hauer authored
The v2 controller has a totally different mechanism to check whether the data we read had ecc errors or not. Implement this. The mechanism in the v2 controller happens to be identical to the v3 controller. Signed-off-by:
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Sascha Hauer authored
This prepares the driver for v3 support. The v3 controller has a completely different register layout, so add a V1_V2_ namespace to the register defines to avoid confusion with the v3 regs. Signed-off-by:
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Sascha Hauer authored
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Sascha Hauer authored
This patch prepares the driver to add v3 controller support later. The v3 controller is basically the same controller as v1 and v2, but with a completely different register layout. Signed-off-by:
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Sascha Hauer authored
We save/restore the value in the buffer anyway, so it makes no difference whether we use main_area0 or main_area1. So, we can use main_area0 and remove main_area1 from the driver which is otherwise unused. Also, clean up the comments in get_dev_status. Signed-off-by:
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Sascha Hauer authored
Add the offset to the register base instead. This is done in preparation for v3 controller support. Signed-off-by:
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Chuanxiao Dong authored
Signed-off-by:
Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by:
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Chuanxiao Dong authored
set_ecc_config function only set ECC_CORRECTION register, so move register setting to probe function. Since controller only support 15bit and 8bit ecc correction, updated nand ecc layout information. Signed-off-by:
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Chuanxiao Dong authored
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Chuanxiao.Dong authored
Hi David, I sent 4 patches using my intel email account. If there is any problem about the format of these patches, I will resend them after I arrived at home by using my gmail account, and I will keep on using gmail account to send patches. Thanks. >From 242e3bf5e17f54b1df8cf285154a7c7a61ff62e9 Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <chuanxiao.dong@intel.com> Date: Fri, 6 Aug 2010 15:29:41 +0800 Subject: [PATCH 1/4] mtd: denali: Remove device_info_tag structure. Most of the variables in this structure are useless, so just remove this structure and relevant codes. Signed-off-by:
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Gabor Juhos authored
Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Signed-off-by:
Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
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Gabor Juhos authored
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Gabor Juhos authored
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Guillaume LECERF authored
The Spansion S29WS-P device family uses CFI version 1.4 [1]. Consider it as a valid version. [1] http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdfSigned-off-by:
Guillaume LECERF <glecerf@gmail.com> Signed-off-by:
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Andreas Bießmann authored
This patch fixes drivers/mtd/nand/atmel_nand.c:372: warning: 'part_probes' defined but not used which is issued when CONFIG_MTD_PARTITIONS is defined but CONFIG_MTD_CMDLINE_PARTS not. Signed-off-by:
Andreas Bießmann <biessmann@corscience.de> Signed-off-by:
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Stefani Seibold authored
This patch prevent to schedule while atomic by changing the flchip_shared spinlock into a mutex. This should be save since no atomic path will use this lock. It was suggested by Arnd Bergmann and Vasiliy Kulikov. Signed-off-by:
Stefani Seibold <stefani@seibold.net> Signed-off-by:
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David Miller authored
Signed-off-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
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Marek Vasut authored
This patch corrects a problem where gen_nand driver assumed there can be only one chip and ignored the pdata->chip.nr_chips value. Signed-off-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
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Maxim Levitsky authored
I think that scary description can go now... Signed-off-by:
Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by:
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Maxim Levitsky authored
Remove the attributes group before disk to avoid use after free Signed-off-by:
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- 05 Aug, 2010 14 commits
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Chuanxiao Dong authored
In denali driver, wTotalBlocks variable is useless, so just remove them in get_toshiba_nand_para and get_hynix_nand_para first. Other wTotalBlocks in denali.c and other variables in dev_info struct are also useless, will remove them later. Also add a parameter in get_hynix_nand_para to prepare to remove dev_info struct. This parameter comes by reading NAND ID directly. Reading register will report wrong value for some NAND chips, e.g. some Micron MT29F32G08QAA chips. So update NAND_CMD_READID method as well. Signed-off-by:
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Chuanxiao Dong authored
rename these functions' name and remove additional declarations in header file Signed-off-by:
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Chuanxiao Dong authored
Signed-off-by:
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Chuanxiao Dong authored
Signed-off-by:
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Chuanxiao Dong authored
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Chuanxiao Dong authored
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Chuanxiao authored
Hi, I have changed the outlook mail cliet to be linux mutt client and use my personal gmail to submit patches. Here are 5 new patches to fix nand/denali check patch errors. The other 4 patches will be sent out after this mail. Thanks for your review. >From d125ad3f57bbf517131dccad6b5933edf8c2632a Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <chuanxiao.dong@intel.com> Date: Tue, 3 Aug 2010 15:54:48 +0800 Subject: [PATCH 1/5] mtd: denali.c: clean up all whitespaces in code indent Signed-off-by:
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Barry Song authored
The IRQSTAT register is a W1C register used by the interrupt handler and may have its BUSY bit changed. This makes it somewhat unreliable for the polling devready function. So switch it over to use the BUSY bit in the STAT register that always reflects the current state of the hardware. This fixes driver hangs seen when the NAND flash is under heavy system load (like I/O benchmarks). Signed-off-by:
Barry Song <barry.song@analog.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
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Barry Song authored
Rather than forcing the platform resources to declare the desired page size, simply use the existing information passed down to us by the higher layers. This way we work out of the box with all flash chips that the kernel knows about. Signed-off-by:
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Barry Song authored
When resetting the ECC registers/counters, the bit will automatically clear itself once the reset has actually finished. So make sure we wait for that to occur before doing anything else rather than assuming everything is peachy and proceeding with stale ECC values. Signed-off-by:
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Barry Song authored
We used the platform rd_dly field when we meant to use the wr_dly field. Signed-off-by:
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Barry Song authored
The NAND base may send some controls which are neither CLE nor ALE, so we need to explicitly check both instead of assuming things are always one or the other. Otherwise, we sometimes send out illegal addresses to the NAND device. Signed-off-by:
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Barry Song authored
Our write_buf/read_buf funcs always do ECC in HW ECC mode. That is not needed for raw funcs. In fact, write_buf/read_buf should be a pure func for data input/output while chip->ecc.hwctl controls ECC. Unfortunately, we can't separate ECC from normal data input/output in our NFC, so our DMA write_buf/read_buf entries are coupled with ECC operations closely. Thus we need to provide dedicated read_page_raw/write_page_raw funcs where we do non-DMA transactions so as to avoid automatic ECC. Signed-off-by:
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Barry Song authored
The low level NAND driver doesn't care about filesystems, so punt the local comment indicating otherwise. Signed-off-by:
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- 04 Aug, 2010 5 commits
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Guillaume LECERF authored
Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3 [1][2]. Fix the check in cfi_cmdset_0002 accordingly. [1] http://www.amd.com/us-en/assets/content_type/DownloadableAssets/cfi_r20.pdf, page 19 [2] http://www.amd.com/us-en/assets/content_type/DownloadableAssets/cfi_100_20011201.pdfSigned-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
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Anton Vorontsov authored
spi_write_then_read() may return its own return codes (e.g. -EIO), so let's propagate the value down to the probe(). Also, remove jedec == 0 check, it isn't needed as nowadays we use dedicated SPI device IDs for non-JEDEC flashes. Suggested-by:
Barry Song <21cnbao@gmail.com> Signed-off-by:
Anton Vorontsov <avorontsov@mvista.com> Acked-by:
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Anton Vorontsov authored
Since commit 18c6182b ("Rework probing/JEDEC code"), m25p80 driver successfully registers chips even if JEDEC probing fails. This was needed to support non-JEDEC flashes. Though, it appears that some platforms (e.g. blackfin bf533 stamp[1]) used the old behavior to detect if there's any flash connected, so the driver have to fail on JEDEC probing errors. This patch restores the old behavior for JEDEC flashes, and adds "-nonjedec" SPI device IDs for M25Pxx flashes, so that the kernel still supports non-JEDEC flashes. [1] http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=5975 Reported-by: Mingquan Pan Reported-by:
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Anatolij Gustschin authored
For no-mmu systems mmap() on RAM/ROM devices already works but for systems with mmu it probably was not tested and doesn't work. This patch allows using mmap() on MTD RAM/ROM devices on systems with MMU. It has been tested on mpc5121e based platform with MR0A16A MRAM device attached over LocalBus. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Acked-by:
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Richard Cochran authored
This patch adds support for static flash partitioning from a platform device. Also, we clean up some weirdness where statements were separated by commas instead of semicolons. While we are at it, fix some minor bad white space, too. Signed-off-by:
Richard Cochran <richard.cochran@omicron.at> Signed-off-by:
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