- 24 Nov, 2014 40 commits
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Kevin Cernekee authored
Add myself as a maintainer for the new BMIPS target. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jfraser@broadcom.com Cc: dtor@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8505/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Prem Karat authored
Based on commit 1091458d (mmap randomization) For 32-bit address spaces randomize within a 16MB space, for 64-bit within a 256MB space. Test Results: ------------ Without Patch (VDSO is not randomized) --------------------------------------- root@Maleo:~# ./aslr vdso FAIL: ASLR not functional (vdso always at 0x7fff7000) root@Maleo:~# ./aslr rekey vdso pre_val==cur_val value=0x7fff7000 With patch:(VDSO is randmoized and doesn't interfere with stack) ---------------------------------------------------------------- root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7f830ea2 current_value=0x776e2000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7fb0cea2 current_value=0x77209000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7f985ea2 current_value=0x7770c000 root@cavium-octeon2:~# ./aslr rekey vdso pre_val!=cur_val previous_value=0x7fbc6ea2 current_value=0x7fe25000 Maps file output: ------------------------- root@cavium-octeon2:~# ./aslr rekey maps 78584000-785a5000 rwxp 00000000 00:00 0 [heap] 7f9d0000-7f9f1000 rw-p 00000000 00:00 0 [stack] 7ffa5000-7ffa6000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 77de0000-77e01000 rwxp 00000000 00:00 0 [heap] 7f91b000-7f93c000 rw-p 00000000 00:00 0 [stack] 7ff99000-7ff9a000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 77d7f000-77da0000 rwxp 00000000 00:00 0 [heap] 7fc2a000-7fc4b000 rw-p 00000000 00:00 0 [stack] 7fe09000-7fe0a000 r-xp 00000000 00:00 0 [vdso] root@cavium-octeon2:~# ./aslr rekey maps 7794c000-7794d000 r-xp 00000000 00:00 0 [vdso] 77e4b000-77e6c000 rwxp 00000000 00:00 0 [heap] 7f6e7000-7f708000 rw-p 00000000 00:00 0 [stack] root@cavium-octeon2:~# Signed-off-by:
Prem Karat <pkarat@mvista.com> Cc: linux-mips@linux-mips.org Cc: sergei.shtylyov@cogentembedded.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6812Signed-off-by:
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Ralf Baechle authored
Signed-off-by:
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Maarten ter Huurne authored
Signed-off-by:
Maarten ter Huurne <maarten@treewalker.org> Cc: Apelete Seketeli <apelete@seketeli.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7671/Signed-off-by:
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Maciej W. Rozycki authored
Signed-off-by:
Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8484/Signed-off-by:
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Maciej W. Rozycki authored
Fix the issue with the ISA bit being lost in fixups that jump to labels placed just before a section switch. Such a switch leads to the ISA bit being lost, because GAS concludes there is no code that follows and therefore the label refers to data. Use the `.insn' pseudo-op to convince the tool this is not the case. This lack of label annotation leads to microMIPS compilation errors like: mips-linux-gnu-ld: arch/mips/built-in.o: .fixup+0x3b8: Unsupported jump between ISA modes; consider recompiling with interlinking enabled. mips-linux-gnu-ld: final link failed: Bad value Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8483/Signed-off-by:
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Maciej W. Rozycki authored
In the microMIPS encoding some memory access instructions have their immediate offset reduced to 12 bits only. That does not match the GCC `R' constraint we use in some places to satisfy the requirement, resulting in build failures like this: {standard input}: Assembler messages: {standard input}:720: Error: macro used $at after ".set noat" {standard input}:720: Warning: macro instruction expanded into multiple instructions Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to the right constraint depending on whether microMIPS or standard MIPS code is produced. Also apply the fix to where `m' is used as in the worst case this change does nothing, e.g. where the pointer was already in a register such as a function argument and no further offset was requested, and in the best case it avoids an extraneous sequence of up to two instructions to load the high 20 bits of the address in the LL/SC loop. This reduces the risk of lock contention that is the higher the more instructions there are in the critical section between LL and SC. Strictly speaking we could just bulk-replace `R' with `ZC' as the latter constraint adjusts automatically depending on the ISA selected. However it was only introduced with GCC 4.9 and we keep supporing older compilers for the standard MIPS configuration, hence the slightly more complicated approach I chose. The choice of a zero-argument function-like rather than an object-like macro was made so that it does not look like a function call taking the C expression used for the constraint as an argument. This is so as not to confuse the reader or formatting checkers like `checkpatch.pl' and follows previous practice. Signed-off-by: -
Maciej W. Rozycki authored
Only allow 32-bit microMIPS builds, we're not ready yet for 64-bit microMIPS support. QEMU does have support for the 64-bit microMIPS ISA and with minor tweaks it is possible to have a 64-bit processor emulated there that runs microMIPS code, so despite the lack of actual 64-bit microMIPS hardware there is a way to run 64-bit microMIPS Linux, but it can all be considered early development and we are not there yet. Userland tools are lacking too, e.g. GCC produces bad code: {standard input}: Assembler messages: {standard input}:380: Warning: wrong size instruction in a 16-bit branch delay slot And our build fails early on, so disable the configuration, for the sake of automatic random config checkers if nothing else. Whoever needs to experiment with 64-bit microMIPS support can revert this change easily. Signed-off-by: -
Maciej W. Rozycki authored
Fix: arch/mips/kernel/signal.c: In function 'handle_signal': arch/mips/kernel/signal.c:533:21: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] unsigned int tmp = (unsigned int)current->mm->context.vdso; ^ arch/mips/kernel/signal.c:536:9: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] vdso = (void *)tmp; ^ cc1: all warnings being treated as errors when building a 64-bit kernel. This is not really a supported configuration, but the cast is wrong either way, Linux makes the assumption that sizeof(void *) equals sizeof(unsigned long) and therefore the latter type is expected to be used where integer operations have to be applied to pointers for some reason. Signed-off-by: -
Maciej W. Rozycki authored
The microMIPS microassembler is only suitable for configurations where the kernel itself is built to microMIPS machine code and not where only user microMIPS software is supported. The former is controlled with the CPU_MICROMIPS configuration setting, whereas SYS_SUPPORTS_MICROMIPS is used for the latter. Not only that, but with a given microMIPS vs standard MIPS kernel configuration only one microassembler is needed, that matches the ISA selected -- CP0.Config3.ISAOnExc is mandatory on microMIPS processors, so there is never a need to mix microMIPS and standard MIPS code. Consequently build only the microassembler that matches the ISA selected for the kernel. Signed-off-by:
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Maciej W. Rozycki authored
Add missing microMIPS support to Malta. Currently the kernel only enables support for the instruction set for the SEAD-3 board despite the fact processor features have nothing to do with the board a processor is installed in. In this case there is no way to run microMIPS software in a fully supported way under Linux on QEMU. QEMU supports the emulation of a Malta board, but does not emulate SEAD-3. Linux supports running microMIPS code on a SEAD-3 board, but hardcodes such support to off on an emulated Malta board even if the processor selected has the microMIPS instruction set implemented. Adding support for the SEAD-3 to QEMU is a major project. Flipping a bit in the kernel that shouldn't have been cleared in the first place is a trivial effort. Thus the answer is plain... Signed-off-by:
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Aaro Koskinen authored
Make loongson_rtc_resources static to eliminate the following sparse warning: warning: symbol 'loongson_rtc_resources' was not declared. Should it be static? Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8529/Signed-off-by:
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Aaro Koskinen authored
Add a missing include to eliminate the following sparse warnings: warning: symbol 'prom_init' was not declared. Should it be static? warning: symbol 'prom_free_prom_memory' was not declared. Should it be static? Signed-off-by:
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Aaro Koskinen authored
Make ml2f_reboot static to elimite the following sparse warning: warning: symbol 'ml2f_reboot' was not declared. Should it be static? Signed-off-by:
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Aaro Koskinen authored
Make internal static to eliminate the following sparse warnings: warning: symbol 'ip6_irqaction' was not declared. Should it be static? warning: symbol 'cascade_irqaction' was not declared. Should it be static? Signed-off-by:
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Aaro Koskinen authored
Add a missing include to get rid of the following sparse warning: warning: symbol 'plat_mem_setup' was not declared. Should it be static? Signed-off-by:
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Aaro Koskinen authored
Add a missing include to get rid of the following sparse warnings: warning: symbol 'cs5536_pci_conf_write4' was not declared. Should it be static? warning: symbol 'cs5536_pci_conf_read4' was not declared. Should it be static? Signed-off-by:
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Aaro Koskinen authored
Fix array initializer syntax to get rid of the following sparse warnings: "obsolete array initializer, use C99 syntax". Signed-off-by:
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Ralf Baechle authored
Signed-off-by: -
Joshua Kinard authored
Building a 64bit kernel for the SGI O2 (IP32) and the SGI Indy (IP22) uses the 'vmlinux.32' target, which converts the output 64-bit 'vmlinux' image into a 32-bit wrapped image. This is needed for certain revisions of the IP22 and IP32 ARCS PROMs to boot correctly, but this target is missing from the 'archhelp' info that is emitted by 'make help'. Signed-off-by:
Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7991/Signed-off-by:
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Markos Chandras authored
Having #ifdefs just to guard comments is not really helpful so drop them. Moreover, the code wasn't really reached anyway since there is a #ifndef CONFIG_CPU_MIPSR2 on the top of the file. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8513/Signed-off-by:
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Aaro Koskinen authored
Mark octeon_model_get_string() with __init and make internal functions static. Signed-off-by:
Aaro Koskinen <aaro.koskinen@nsn.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7668/Signed-off-by:
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Aaro Koskinen authored
Move code to avoid forward declarations. Signed-off-by:
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Aaro Koskinen authored
We should not need to read fuses during normal operation, also the current code has issues with that (not safe for concurrent access). Since there are no in-kernel users for these, just delete them. Drivers should not need such OCTEON_HAS_FEATURE mechanism in any case, instead the information should be passed via device tree. Signed-off-by:
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Aaro Koskinen authored
Move cvmx_fuse_read_byte() into a .c file. Signed-off-by:
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Aaro Koskinen authored
Continue the backtrace if we cannot find SP adjustment and RA save. In that case, just assume the current RA. This allows us to get samples of frequent callers of e.g. GLIBC memset(). Signed-off-by:
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Aaro Koskinen authored
Allow unsupported CPU types to use backtrace with timer-based profiling. Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In such case oprofile can fallback to timer-based mode, and arch code can still provide the backtrace functionality. So just set up the backtrace hook always. Signed-off-by:
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Markos Chandras authored
They can be useful to determine how the MMU is configured on a MC exception. Signed-off-by:
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Markos Chandras authored
The HTW registers can be useful to debug a MC exception. Signed-off-by:
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Markos Chandras authored
printk should not be used without a KERN_ facility level Signed-off-by:
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Andrew Bresticker authored
Parse the GIC timer frequency and interrupt from the device-tree. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8421/Signed-off-by:
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Andrew Bresticker authored
Add device-tree support for the MIPS GIC. Update the GIC irqdomain's xlate() callback to handle the three-cell specifier described in the MIPS GIC binding document. Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8422/Signed-off-by:
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Andrew Bresticker authored
The Global Interrupt Controller (GIC) present on certain MIPS systems can be used to route external interrupts to individual VPEs and CPU interrupt vectors. It also supports a timer and software-generated interrupts. Signed-off-by:
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Alban Bedel authored
Allow loading an initrd passed by the firmware. Signed-off-by:
Alban Bedel <albeu@free.fr> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8354/Signed-off-by:
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Alban Bedel authored
No need to duplicate code that is available in the firmware library. It also give us access to the firmware environment which is needed to read the initrd address and size. Signed-off-by:
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Sergey Ryazanov authored
Atheros AR5312 and AR2315 both have a builtin wireless device, this patch add helper code and register platform device for all supported WiSoCs. Signed-off-by:
Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8249/Signed-off-by:
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Sergey Ryazanov authored
- Use config symbol defined in the driver instead of arch specific one for conditional compilation. - Rename the ATHEROS_AR231X config symbol to ATH25. - Fix include (ar231x_platform.h -> ath25_platform.h). - Some of AR231x SoCs (e.g. AR2315) have PCI bus support, so remove !PCI dependency, which block AHB support build. Signed-off-by:
John W. Linville <linville@tuxdriver.com> Cc: Jiri Slaby <jirislaby@gmail.com> Cc: Nick Kossifidis <mickflemm@gmail.com> Cc: "Luis R. Rodriguez" <mcgrof@do-not-panic.com> Cc: linux-wireless@vger.kernel.org Cc: ath5k-devel@lists.ath5k.org Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8248/Signed-off-by:
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Sergey Ryazanov authored
This reverts commit 093ec3c5. AHB bus code has been removed, since we did not have support Atheros AR231x SoC, required for building the AHB version of ath5k. Now that support WiSoC chips added we can restore functionality back. Signed-off-by:
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Sergey Ryazanov authored
Add PCI host controller driver and DMA address calculation hook. Signed-off-by:
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Sergey Ryazanov authored
AR5312 SoC flash controller maps the flash content to memory and translates the memory access operations to the flash access operations. Such controller is fully supported by the physmap-flash driver. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>R5312 SoC flash Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8245/Signed-off-by:
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