- 23 Aug, 2019 2 commits
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Kevin Wang authored
fix other navi asic set peak performance level error. because the navi10_ppt.c will handle navi12 14 asic, it will use navi10 peak value to set other asic, it is not correct. after patch: only navi10 use custom peak value, other asic will used default value. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Guchun Chen authored
Use unsigned long type for the same ras count variable. This will avoid overflow on 64 bit system. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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- 22 Aug, 2019 38 commits
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Dmytro Laktyushkin authored
This was broken by a previous change switching to cached fw_info. Fixed by inverting a valid bool check. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111432 Fixes: 9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create") Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Thong Thai authored
This will enable indirect SRAM loading for VCN DPG mode initialization. Signed-off-by:
Thong Thai <thong.thai@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Thong Thai authored
This reverts commit 444a0fea. We are ready to enable it now. Signed-off-by:
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Aaron Liu authored
This patch updates gc/sdma goldensetting for renoir Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Prike Liang authored
To avoid the dpm frequence range get failed when DPM enabled and it will be enabled later once handle well the feature bit map struct. Signed-off-by:
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Prike Liang authored
enable the dpm feature for the renoir. Signed-off-by:
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Prike Liang authored
Enable SDMA PG flag during device ip early init. Reviewed-by:
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Prike Liang authored
Add support for SDMA clockgating on RN. Signed-off-by:
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Prike Liang authored
setup mmhub clockgating. Signed-off-by:
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Prike Liang authored
Enable DF clock gating during DF IP early init. Signed-off-by:
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Prike Liang authored
Enable athub MG and LS clock gating. Signed-off-by:
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Prike Liang authored
Enable IH clock gating during IH block initialized. Signed-off-by:
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Prike Liang authored
Enable VCN middle grain clock gating. Signed-off-by:
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Prike Liang authored
Enable rom light sleep clock gating. Reviewed-by:
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Prike Liang authored
Enable HDP light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable BIF light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable sdma middle grain and light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable mmhub midle grain and light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable gfx cg/mg/cp etc clock gating. Signed-off-by:
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Aaron Liu authored
This patch adds add DPMCLOCKS table implementation Rename smu_populate_smc_pptable to smu_populate_smc_tables Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Aaron Liu authored
Initialize smu tables for renoir: WATERMARKS/DPMCLOCKS/SMU_METRICS Signed-off-by:
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Aaron Liu authored
add and map smu tables for renoir Signed-off-by:
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Aaron Liu authored
Check whether the message mapping is valid Signed-off-by:
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Aaron Liu authored
For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check gfxoff status. For the first time to enter gfxoff status, it maybe takes about one second more. So just set the max timeout to 5s. GFXOFF_STATUS(bits 2:1)'s description is below: 0=GFXOFF(default). 1=Transition out of GFX State. 2=Not in GFXOFF. 3=Transition into GFXOFF. Reviewed-by:
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Aaron Liu authored
This patch updates gfxoff feature. Signed-off-by:
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Aaron Liu authored
add set_gfx_cgpg implement v2: check if using sw_smu (Alex) Signed-off-by:
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Aaron Liu authored
This interface support SMU_MSG_GetDriverIfVersion and SMU_MSG_GetSmuVersion checking. v2: squash in driver_if changes (Alex) Signed-off-by:
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Huang Rui authored
All apu series need powerup sdma and vcn via smu messages. Signed-off-by:
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Leo Liu authored
Thus VCN can be powered up for normal operations Signed-off-by:
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Huang Rui authored
Renoir DPM is not functional so far, we skip it for the comment. Will revert this patch once SMU 12 is functional. Signed-off-by:
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Aaron Liu authored
1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx&sdma ip block Signed-off-by:
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Aaron Liu authored
add swSMU [smu_v12_0] for renoir v2: whitespace fixes (Alex) Signed-off-by:
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Aaron Liu authored
add smu_v12_0.c & smu_v12_0.h for renoir Signed-off-by:
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Aaron Liu authored
Add renoir_ppt and map ppsmc to amdgpu_smu.h v2: squash in ppsmc updates (Alex) v3: squash in driver_if updates (Alex) Signed-off-by:
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Aaron Liu authored
This patch adds smu12_driver_if.h v2: squash in updates (Alex) v3: more updates (Alex) Signed-off-by:
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Alex Deucher authored
This is the SMU v12 driver message interface. v2: squash in updates Signed-off-by: -
Colin Ian King authored
Currently the pointer init_data is dereferenced on the assignment of fw_info before init_data is sanity checked to see if it is null. Fix te potential null pointer dereference on init_data by only performing dereference after it is null checked. Addresses-Coverity: ("Dereference before null check") Fixes: 9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create") Reviewed-by:Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Colin Ian King authored
Variable baco_state is initialized to a value that is never read and it is re-assigned later. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused Value") Signed-off-by:
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