1. 12 Jul, 2008 29 commits
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: MSI and MSI-X support for interrupt remapping infrastructure · 75c46fa6
      Suresh Siddha authored
      MSI and MSI-X support for interrupt remapping infrastructure.
      
      MSI address register will be programmed with interrupt-remapping table
      entry(IRTE) index and the IRTE will contain information about the vector,
      cpu destination, etc.
      
      For MSI-X, all the IRTE's will be consecutively allocated in the table,
      and the address registers will contain the starting index to the block
      and the data register will contain the subindex with in that block.
      
      This also introduces a new irq_chip for cleaner irq migration (in the process
      context as opposed to the current irq migration in the context of an interrupt.
      interrupt-remapping infrastructure will help us achieve this).
      
      As MSI is edge triggered, irq migration is a simple atomic update(of vector
      and cpu destination) of IRTE and flushing the hardware cache.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      75c46fa6
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping · 89027d35
      Suresh Siddha authored
      IO-APIC support in the presence of interrupt-remapping infrastructure.
      
      IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
      index and the IRTE will contain information about the vector, cpu destination,
      trigger mode etc, which traditionally was present in the IO-APIC RTE.
      
      Introduce a new irq_chip for cleaner irq migration (in the process
      context as opposed to the current irq migration in the context of an interrupt.
      interrupt-remapping infrastructure will help us achieve this cleanly).
      
      For edge triggered, irq migration is a simple atomic update(of vector
      and cpu destination) of IRTE and flush the hardware cache.
      
      For level triggered, we need to modify the io-apic RTE aswell with the update
      vector information, along with modifying IRTE with vector and cpu destination.
      So irq migration for level triggered is little  bit more complex compared to
      edge triggered migration. But the good news is, we use the same algorithm
      for level triggered migration as we have today, only difference being,
      we now initiate the irq migration from process context instead of the
      interrupt context.
      
      In future, when we do a directed EOI (combined with cpu EOI broadcast
      suppression) to the IO-APIC, level triggered irq migration will also be
      as simple as edge triggered migration and we can do the irq migration
      with a simple atomic update to IO-APIC RTE.
      
      TBD: some tests/changes needed in the presence of fixup_irqs() for
      level triggered irq migration.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      89027d35
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: setup init_apic_ldr for UV · 5c520a67
      Suresh Siddha authored
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      5c520a67
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: x2apic cluster mode support · 12a67cf6
      Suresh Siddha authored
      x2apic cluster mode support.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      12a67cf6
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: introcude self IPI to genapic routines · cff73a6f
      Suresh Siddha authored
      Introduce self IPI op for genapic.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      cff73a6f
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: x2apic ops for x2apic mode support · 13c88fb5
      Suresh Siddha authored
      x2apic ops for x2apic mode support. This uses MSR interface and differs
      slightly from the xapic register layout.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      13c88fb5
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: disable DMA-remapping if Interrupt-remapping is detected (temporary quirk) · 1cb11583
      Suresh Siddha authored
      Interrupt-remapping enables queued invalidation. And once queued invalidation
      is enabled, IOTLB invalidation also needs to use the queued invalidation
      mechanism and the register based IOTLB invalidation doesn't work.
      
      For now, Support for IOTLB invalidation using queued invalidation is
      missing. Meanwhile, disable DMA-remapping, if Interrupt-remapping
      support is detected.
      
      For the meanwhile, if someone wants to really enable DMA-remapping, they
      can use nox2apic, which will disable interrupt-remapping and as such
      doesn't enable queued invalidation.
      
      And given that none of the release platforms support intr-remapping yet,
      we should be ok for this temporary hack.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      1cb11583
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: cpuid bits for x2apic feature · 32e1d0a0
      Suresh Siddha authored
      cpuid feature for x2apic.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      32e1d0a0
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: basic apic ops support · 1b374e4d
      Suresh Siddha authored
      Introduce basic apic operations which handle the apic programming. This
      will be used later to introduce another specific operations for x2apic.
      
      For the perfomance critial accesses like IPI's, EOI etc, we use the
      native operations as they are already referenced by different
      indirections like genapic, irq_chip etc.
      
      64bit Paravirt ops can also define their apic operations accordingly.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      1b374e4d
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Interrupt-remapping and x2apic support, fix · 2d7a66d0
      Suresh Siddha authored
      Yinghai Lu wrote:
      
      > Setting APIC routing to physical flat
      > Kernel panic - not syncing: Boot APIC ID in local APIC unexpected (0 vs 4)
      > Pid: 1, comm: swapper Not tainted 2.6.26-rc9-tip-01763-g74f94b1-dirty #320
      >
      > Call Trace:
      >  [<ffffffff80a21505>] ? set_cpu_sibling_map+0x38c/0x3bd
      >  [<ffffffff80245215>] ? read_xapic_id+0x25/0x3e
      >  [<ffffffff80e5a2c3>] ? verify_local_APIC+0x139/0x1b9
      >  [<ffffffff80245215>] ? read_xapic_id+0x25/0x3e
      >  [<ffffffff80e589af>] ? native_smp_prepare_cpus+0x224/0x2e9
      >  [<ffffffff80e4881a>] ? kernel_init+0x64/0x341
      >  [<ffffffff8022a439>] ? child_rip+0xa/0x11
      >  [<ffffffff80e487b6>] ? kernel_init+0x0/0x341
      >  [<ffffffff8022a42f>] ? child_rip+0x0/0x11
      >
      >
      > guess read_apic_id changing cuase some problem...
      
      genapic's read_apic_id() returns the actual apic id extracted from
      the APIC_ID register. And in some cases like UV, read_apic_id()
      returns completely different values from APIC ID register.
      
      Use the native apic register read, rather than genapic read_apic_id()
      in verify_local_APIC()
      
      And also, lapic_suspend() should also use native apic register read.
      Reported-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: "akpm@linux-foundation.org" <akpm@linux-foundation.org>
      Cc: "arjan@linux.intel.com" <arjan@linux.intel.com>
      Cc: "andi@firstfloor.org" <andi@firstfloor.org>
      Cc: "ebiederm@xmission.com" <ebiederm@xmission.com>
      Cc: "jbarnes@virtuousgeek.org" <jbarnes@virtuousgeek.org>
      Cc: "steiner@sgi.com" <steiner@sgi.com>
      Cc: "jeremy@goop.org" <jeremy@goop.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      2d7a66d0
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: introduce read_apic_id() to genapic routines · 0c81c746
      Suresh Siddha authored
      Move the read_apic_id()  to genapic routines.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      0c81c746
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: ioapic routines which deal with initial io-apic RTE setup · 4dc2f96c
      Suresh Siddha authored
      Generic ioapic specific routines which be used later during enabling
      interrupt-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      4dc2f96c
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: 8259 specific mask/unmask routines · d94d93ca
      Suresh Siddha authored
      8259 specific mask/unmask routines which be used later while enabling
      interrupt-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      d94d93ca
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: generic irq migration support from process context · 72b1e22d
      Suresh Siddha authored
      Generic infrastructure for migrating the irq from the process context in the
      presence of CONFIG_GENERIC_PENDING_IRQ.
      
      This will be used later for migrating irq in the presence of
      interrupt-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      72b1e22d
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: routines managing Interrupt remapping table entries. · b6fcb33a
      Suresh Siddha authored
      Routines handling the management of interrupt remapping table entries.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      b6fcb33a
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Interrupt remapping infrastructure · 2ae21010
      Suresh Siddha authored
      Interrupt remapping (part of Intel Virtualization Tech for directed I/O)
      infrastructure.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      2ae21010
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Queued invalidation infrastructure (part of VT-d) · fe962e90
      Suresh Siddha authored
      Queued invalidation (part of Intel Virtualization Technology for
      Directed I/O architecture) infrastructure.
      
      This will be used for invalidating the interrupt entry cache in the
      case of Interrupt-remapping and IOTLB invalidation in the case
      of DMA-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      fe962e90
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: move IOMMU_WAIT_OP() macro to intel-iommu.h · cf1337f0
      Suresh Siddha authored
      move IOMMU_WAIT_OP() macro to header file.
      
      This will be used by both DMA-remapping and Intr-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      cf1337f0
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: parse ioapic scope under vt-d structures · ad3ad3f6
      Suresh Siddha authored
      Parse the vt-d device scope structures to find the mapping between IO-APICs
      and the interrupt remapping hardware units.
      
      This will be used later for enabling Interrupt-remapping for IOAPIC devices.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      ad3ad3f6
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Fix the need for RMRR in the DMA-remapping detection · 2d6b5f85
      Suresh Siddha authored
      Presence of RMRR structures is not compulsory for enabling DMA-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: default avatarYong Y Wang <yong.y.wang@intel.com>
      Cc: Yong Y Wang <yong.y.wang@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      2d6b5f85
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: use CONFIG_DMAR for DMA-remapping specific code · aaa9d1dd
      Suresh Siddha authored
      DMA remapping specific code covered with CONFIG_DMAR in
      the generic code which will also be used later for enabling Interrupt-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      aaa9d1dd
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: code re-structuring, to be used by both DMA and Interrupt remapping · 1886e8a9
      Suresh Siddha authored
      Allocate the iommu during the parse of DMA remapping hardware
      definition structures. And also, introduce routines for device
      scope initialization which will be explicitly called during
      dma-remapping initialization.
      
      These will be used for enabling interrupt remapping separately from the
      existing DMA-remapping enabling sequence.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      1886e8a9
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: fix the need for sequential array allocation of iommus · c42d9f32
      Suresh Siddha authored
      Clean up the intel-iommu code related to deferred iommu flush logic. There is
      no need to allocate all the iommu's as a sequential array.
      
      This will be used later in the interrupt-remapping patch series to
      allocate iommu much early and individually for each device remapping
      hardware unit.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      c42d9f32
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Intel vt-d, IOMMU code reorganization · e61d98d8
      Suresh Siddha authored
      code reorganization of the generic Intel vt-d parsing related routines and linux
      iommu routines specific to Intel vt-d.
      
      drivers/pci/dmar.c	now contains the generic vt-d parsing related routines
      drivers/pci/intel_iommu.c contains the iommu routines specific to vt-d
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      e61d98d8
    • Ingo Molnar's avatar
      Merge branch 'x86/core' into x86/x2apic · 1ba89386
      Ingo Molnar authored
      1ba89386
    • Ingo Molnar's avatar
      Merge branch 'linus' into x86/core · ae94b807
      Ingo Molnar authored
      Conflicts:
      
      	arch/x86/mm/ioremap.c
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      ae94b807
    • Roland McGrath's avatar
      x86_64: fix delayed signals · eca91e78
      Roland McGrath authored
      On three of the several paths in entry_64.S that call
      do_notify_resume() on the way back to user mode, we fail to properly
      check again for newly-arrived work that requires another call to
      do_notify_resume() before going to user mode.  These paths set the
      mask to check only _TIF_NEED_RESCHED, but this is wrong.  The other
      paths that lead to do_notify_resume() do this correctly already, and
      entry_32.S does it correctly in all cases.
      
      All paths back to user mode have to check all the _TIF_WORK_MASK
      flags at the last possible stage, with interrupts disabled.
      Otherwise, we miss any flags (TIF_SIGPENDING for example) that were
      set any time after we entered do_notify_resume().  More work flags
      can be set (or left set) synchronously inside do_notify_resume(), as
      TIF_SIGPENDING can be, or asynchronously by interrupts or other CPUs
      (which then send an asynchronous interrupt).
      
      There are many different scenarios that could hit this bug, most of
      them races.  The simplest one to demonstrate does not require any
      race: when one signal has done handler setup at the check before
      returning from a syscall, and there is another signal pending that
      should be handled.  The second signal's handler should interrupt the
      first signal handler before it actually starts (so the interrupted PC
      is still at the handler's entry point).  Instead, it runs away until
      the next kernel entry (next syscall, tick, etc).
      
      This test behaves correctly on 32-bit kernels, and fails on 64-bit
      (either 32-bit or 64-bit test binary).  With this fix, it works.
      
          #define _GNU_SOURCE
          #include <stdio.h>
          #include <signal.h>
          #include <string.h>
          #include <sys/ucontext.h>
      
          #ifndef REG_RIP
          #define REG_RIP REG_EIP
          #endif
      
          static sig_atomic_t hit1, hit2;
      
          static void
          handler (int sig, siginfo_t *info, void *ctx)
          {
            ucontext_t *uc = ctx;
      
            if ((void *) uc->uc_mcontext.gregs[REG_RIP] == &handler)
              {
                if (sig == SIGUSR1)
                  hit1 = 1;
                else
                  hit2 = 1;
              }
      
            printf ("%s at %#lx\n", strsignal (sig),
                    uc->uc_mcontext.gregs[REG_RIP]);
          }
      
          int
          main (void)
          {
            struct sigaction sa;
            sigset_t set;
      
            sigemptyset (&sa.sa_mask);
            sa.sa_flags = SA_SIGINFO;
            sa.sa_sigaction = &handler;
      
            if (sigaction (SIGUSR1, &sa, NULL)
                || sigaction (SIGUSR2, &sa, NULL))
              return 2;
      
            sigemptyset (&set);
            sigaddset (&set, SIGUSR1);
            sigaddset (&set, SIGUSR2);
            if (sigprocmask (SIG_BLOCK, &set, NULL))
              return 3;
      
            printf ("main at %p, handler at %p\n", &main, &handler);
      
            raise (SIGUSR1);
            raise (SIGUSR2);
      
            if (sigprocmask (SIG_UNBLOCK, &set, NULL))
              return 4;
      
            if (hit1 + hit2 == 1)
              {
                puts ("PASS");
                return 0;
              }
      
            puts ("FAIL");
            return 1;
          }
      Signed-off-by: default avatarRoland McGrath <roland@redhat.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      eca91e78
    • Rafael J. Wysocki's avatar
      x86: remove conflicting nx6325 and nx6125 quirks · da1f29f5
      Rafael J. Wysocki authored
      We have two conflicting DMA-based quirks in there for the same set of
      boxes (HP nx6325 and nx6125) and one of them actually breaks my box.
      
      So remove the extra code.
      Signed-off-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Cc: =?iso-8859-1?q?T=F6r=F6k_Edwin?= <edwintorok@gmail.com>
      Cc: Vegard Nossum <vegard.nossum@gmail.com>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      da1f29f5
    • Linus Torvalds's avatar
  2. 11 Jul, 2008 11 commits
    • Mark Rustad's avatar
      [PATCH] IPMI: return correct value from ipmi_write · 3976df9b
      Mark Rustad authored
      This patch corrects the handling of write operations to the IPMI watchdog
      to work as intended by returning the number of characters actually
      processed. Without this patch, an "echo V >/dev/watchdog" enables the
      watchdog if IPMI is providing the watchdog function.
      Signed-off-by: default avatarMark Rustad <MRustad@gmail.com>
      Signed-off-by: default avatarCorey Minyard <cminyard@mvista.com>
      Signed-off-by: default avatarWim Van Sebroeck <wim@iguana.be>
      3976df9b
    • Ingo Molnar's avatar
      6c82a000
    • Maciej W. Rozycki's avatar
      x86: Recover timer_ack lost in the merge of the NMI watchdog · 5b4d2386
      Maciej W. Rozycki authored
      In the course of the recent unification of the NMI watchdog an assignment
      to timer_ack to switch off unnecesary POLL commands to the 8259A in the
      case of a watchdog failure has been accidentally removed.  The statement
      used to be limited to the 32-bit variation as since the rewrite of the
      timer code it has been relevant for the 82489DX only.  This change brings
      it back.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      5b4d2386
    • Maciej W. Rozycki's avatar
      x86: I/O APIC: Never configure IRQ2 · af174783
      Maciej W. Rozycki authored
      There is no such entity as ISA IRQ2.  The ACPI spec does not make it
      explicitly clear, but does not preclude it either -- all it says is ISA
      legacy interrupts are identity mapped by default (subject to overrides),
      but it does not state whether IRQ2 exists or not.  As a result if there is
      no IRQ0 override, then IRQ2 is normally initialised as an ISA interrupt,
      which implies an edge-triggered line, which is unmasked by default as this
      is what we do for edge-triggered I/O APIC interrupts so as not to miss an
      edge.
      
      To the best of my knowledge it is useless, as IRQ2 has not been in use
      since the PC/AT as back then it was taken by the 8259A cascade interrupt
      to the slave, with the line position in the slot rerouted to newly-created
      IRQ9.  No device could thus make use of this line with the pair of 8259A
      chips.  Now in theory INTIN2 of the I/O APIC may be usable, but the
      interrupt of the device wired to it would not be available in the PIC mode
      at all, so I seriously doubt if anybody decided to reuse it for a regular
      device.
      
      However there are two common uses of INTIN2.  One is for IRQ0, with an
      ACPI interrupt override (or its equivalent in the MP table).  But in this
      case IRQ2 is gone entirely with INTIN0 left vacant.  The other one is for
      an 8959A ExtINTA cascade.  In this case IRQ0 goes to INTIN0 and if ACPI is
      used INTIN2 is assumed to be IRQ2 (there is no override and ACPI has no
      way to report ExtINTA interrupts).  This is where a problem happens.
      
      The problem is INTIN2 is configured as a native APIC interrupt, with a
      vector assigned and the mask cleared.  And the line may indeed get active
      and inject interrupts if the master 8959A has its timer interrupt enabled
      (it might happen for other interrupts too, but they are normally masked in
      the process of rerouting them to the I/O APIC).  There are two cases where
      it will happen:
      
      * When the I/O APIC NMI watchdog is enabled.  This is actually a misnomer
        as the watchdog pulses are delivered through the 8259A to the LINT0
        inputs of all the local APICs in the system.  The implication is the
        output of the master 8259A goes high and low repeatedly, signalling
        interrupts to INTIN2 which is enabled too!
      
        [The origin of the name is I think for a brief period during the
        development we had a capability in our code to configure the watchdog to
        use an I/O APIC input; that would be INTIN2 in this scenario.]
      
      * When the native route of IRQ0 via INTIN0 fails for whatever reason -- as
        it happens with the system considered here.  In this scenario the timer
        pulse is delivered through the 8259A to LINT0 input of the local APIC of
        the bootstrap processor, quite similarly to how is done for the watchdog
        described above.  The result is, again, INTIN2 receives these pulses
        too.  Rafael's system used to escape this scenario, because an incorrect
        IRQ0 override would occupy INTIN2 and prevent it from being unmasked.
      
      My conclusion is IRQ2 should be excluded from configuration in all the
      cases and the current exception for ACPI systems should be lifted.  The
      reason being the exception not only being useless, but harmful as well.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      af174783
    • Maciej W. Rozycki's avatar
      x86: L-APIC: Always fully configure IRQ0 · c88ac1df
      Maciej W. Rozycki authored
      Unlike the 32-bit one, the 64-bit variation of the LVT0 setup code for
      the "8259A Virtual Wire" through the local APIC timer configuration does
      not fully configure the relevant irq_chip structure.  Instead it relies on
      the preceding I/O APIC code to have set it up, which does not happen if
      the I/O APIC variants have not been tried.
      
      The patch includes corresponding changes to the 32-bit variation too
      which make them both the same, barring a small syntactic difference
      involving sequence of functions in the source.  That should work as an aid
      with the upcoming merge.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      c88ac1df
    • Maciej W. Rozycki's avatar
      x86: L-APIC: Set IRQ0 as edge-triggered · 1baea6e2
      Maciej W. Rozycki authored
       IRQ0 is edge-triggered, but the "8259A Virtual Wire" through the local
      APIC configuration in the 32-bit version uses the "fasteoi" handler
      suitable for level-triggered APIC interrupt.  Rewrite code so that the
      "edge" handler is used.  The 64-bit version uses different code and is
      unaffected.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      1baea6e2
    • Glauber Costa's avatar
      x86: merge dwarf2 headers · 392a0fc9
      Glauber Costa authored
      Merge dwarf2_32.h and dwarf2_64.h into dwarf2.h.
      Signed-off-by: default avatarGlauber Costa <gcosta@redhat.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      392a0fc9
    • Glauber Costa's avatar
      x86: use AS_CFI instead of UNWIND_INFO · d73a731a
      Glauber Costa authored
      In dwarf2_32.h, test for CONFIG_AS_CFI instead of
      CONFIG_UNWIND_INFO. Turns out that searching for UNWIND_INFO
      returns no match in any Kconfig or Makefile, so we're really
      just throwing everything away regarding dwarf frames for i386.
      
      The test that generates CONFIG_AS_CFI does not have anything
      x86_64-specific, and right now, checking V=1 builds shows me
      that the flags is there anyway, although unused.
      Signed-off-by: default avatarGlauber Costa <gcosta@redhat.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      d73a731a
    • Glauber Costa's avatar
      x86: use ignore macro instead of hash comment · 70f1bba4
      Glauber Costa authored
      In dwarf_64.h header, use the "ignore" macro the way
      i386 does.
      Signed-off-by: default avatarGlauber Costa <gcosta@redhat.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      70f1bba4
    • Glauber Costa's avatar
      x86: use matching CFI_ENDPROC · 557d7d4e
      Glauber Costa authored
      The RING0_INT_FRAME macro defines a CFI_STARTPROC.
      So we should really be using CFI_ENDPROC after it.
      Signed-off-by: default avatarGlauber Costa <gcosta@redhat.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      557d7d4e
    • Linus Torvalds's avatar
      Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev · 4d727a78
      Linus Torvalds authored
      * 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
        libata-acpi: don't call sleeping function from invalid context
        Added Targa Visionary 1000 IDE adapter to pata_sis.c
        libata-acpi: filter out DIPM enable
      4d727a78