- 13 May, 2016 40 commits
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Matt Redfearn authored
This tool is based on the x86/boot/tools/relocs tool. It parses the relocations present in the vmlinux elf file, building a table of relocations that will be necessary to run the kernel from an address other than its link address. This table is inserted into the vmlinux elf, in the .data.relocs section. The table is subsequently used by the code in arch/mips/kernel/relocate.c (added later) to relocate the kernel. The tool, by default, also marks all relocation sections as 0 length. This is due to objcopy currently being unable to handle copying the relocations between 64 and 32 bit elf files as is done when building a 64 bit kernel. Signed-off-by:
Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kernel-hardening@lists.openwall.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12981/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Matt Redfearn authored
These values are constant and should be marked as such. Signed-off-by:
Kees Cook <keescook@chromium.org> Cc: Will Drewry <wad@chromium.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: IMG-MIPSLinuxKerneldevelopers@imgtec.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12979/Signed-off-by:
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Matt Redfearn authored
Previously the seccomp would only support strict mode on O32 userland programs when the kernel had support for both O32 and N32 ABIs. Remove kludge and support both ABIs. With this patch in place, the seccomp_bpf self test now passes global.mode_strict_support with N32 userland. Suggested-by:
Paul Burton <paul.burton@imgtec.com> Signed-off-by:
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Matt Redfearn authored
Move retrieval of compat syscall numbers into inline function defined in asm-generic header so that arches may override it. [ralf@linux-mips.org: Resolve merge conflict.] Suggested-by:
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Matt Redfearn authored
Commit d218af78 ("MIPS: scall: Always run the seccomp syscall filters") modified the syscall code to always call the seccomp filters, but missed the case where a filter may redirect the syscall, as revealed by the seccomp_bpf self test. The syscall path now restores the syscall from the stack after the filter rather than saving it locally. Syscall number checking and syscall function table lookup is done after the filter may have run such that redirected syscalls are also checked, and executed. The regular path of syscall number checking and pointer lookup is also made more consistent between ABIs with scall64-64.S being the reference. With this patch in place, the seccomp_bpf self test now passes TRACE_syscall.syscall_redirected and TRACE_syscall.syscall_dropped on all MIPS ABIs. Fixes: d218af78 ("MIPS: scall: Always run the seccomp syscall filters") Signed-off-by:
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Matt Redfearn authored
The seccomp_bpf self test revealed that a 64bit kernel delivered an invalid SIG_SYS to a 32bit userspace, because it was falling into the default of the switch statement. Add a case to handle delivering the signal. With this patch, the seccomp_bpf self test now passes the TRAP.handler case with O32 and N32 userlands. Signed-off-by:
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Matt Redfearn authored
This adds self-test support on MIPS, based on RFC patch from Kees Cook. Modifications from the RFC: - support the O32 syscall which passes the real syscall number in a0. - Use PTRACE_{GET,SET}REGS - Because SYSCALL_NUM and SYSCALL_RET are the same register, it is not possible to test modifying the syscall return value when skipping, since both would need to set the same register. Therefore modify that test case to just detect the skipped test. Tested on MIPS32r2 / MIPS64r2 with O32, N32 and N64 userlands. Signed-off-by: -
Martin Schiller authored
This patch updates the compatible string in the easy50712.dts file to the new "lantiq,danube-pinctrl". Signed-off-by:
Martin Schiller <mschiller@tdt.de> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Cc: robh+dt@kernel.org Cc: pawel.moll@arm.com Cc: mark.rutland@arm.com Cc: ijc+devicetree@hellion.org.uk Cc: galak@codeaurora.org Cc: john@phrozen.org Cc: hauke@hauke-m.de Cc: jogo@openwrt.org Cc: daniel.schwierzeck@gmail.com Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11589/Signed-off-by:
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Daniel Wagner authored
parse_crash_elf{32|64}_headers will check the headers via the elf_check_arch respectively vmcore_elf64_check_arch macro. The MIPS architecture implements those two macros differently. In order to make the differentiation more explicit, let's introduce an vmcore_elf32_check_arch to allow the archs to overwrite it. Signed-off-by:Daniel Wagner <daniel.wagner@bmw-carit.de> Suggested-by:
Maciej W. Rozycki <macro@imgtec.com> Reviewed-by:
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Simon Arlott authored
Add device tree binding for the BCM6345 interrupt controller. This controller is similar to the SMP-capable BCM7038 and the BCM3380 but with packed interrupt registers. Signed-off-by:
Simon Arlott <simon@fire.lp0.eu> Acked-by:
Rob Herring <robh@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11804/Signed-off-by:
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Borislav Petkov authored
Option is long gone, see 5d9efa7e ("ipv6: Remove privacy config option.") Signed-off-by:
Borislav Petkov <bp@suse.de> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/12919/Signed-off-by:
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Stephen Boyd authored
The generic header file is equivalent to the MIPS one, so use the generic one instead. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12261/Signed-off-by:
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Paul Burton authored
It's possible for pages to become visible prior to update_mmu_cache running if a thread within the same address space preempts the current thread or runs simultaneously on another CPU. That is, the following scenario is possible: CPU0 CPU1 write to page flush_dcache_page flush_icache_page set_pte_at map page update_mmu_cache If CPU1 maps the page in between CPU0's set_pte_at, which marks it valid & visible, and update_mmu_cache where the dcache flush occurs then CPU1s icache will fill from stale data (unless it fills from the dcache, in which case all is good, but most MIPS CPUs don't have this property). Commit 4d46a67a ("MIPS: Fix race condition in lazy cache flushing.") attempted to fix that by performing the dcache flush in flush_icache_page such that it occurs before the set_pte_at call makes the page visible. However it has the problem that not all code that writes to pages exposed to userland call flush_icache_page. There are many callers of set_pte_at under mm/ and only 2 of them do call flush_icache_page. Thus the race window between a page becoming visible & being coherent between the icache & dcache remains open in some cases. To illustrate some of the cases, a WARN was added to __update_cache with this patch applied that triggered in cases where a page about to be flushed from the dcache was not the last page provided to flush_icache_page. That is, backtraces were obtained for cases in which the race window is left open without this patch. The 2 standout examples follow. When forking a process: [ 15.271842] [<80417630>] __update_cache+0xcc/0x188 [ 15.277274] [<80530394>] copy_page_range+0x56c/0x6ac [ 15.282861] [<8042936c>] copy_process.part.54+0xd40/0x17ac [ 15.289028] [<80429f80>] do_fork+0xe4/0x420 [ 15.293747] [<80413808>] handle_sys+0x128/0x14c When exec'ing an ELF binary: [ 14.445964] [<80417630>] __update_cache+0xcc/0x188 [ 14.451369] [<80538d88>] move_page_tables+0x414/0x498 [ 14.457075] [<8055d848>] setup_arg_pages+0x220/0x318 [ 14.462685] [<805b0f38>] load_elf_binary+0x530/0x12a0 [ 14.468374] [<8055ec3c>] search_binary_handler+0xbc/0x214 [ 14.474444] [<8055f6c0>] do_execveat_common+0x43c/0x67c [ 14.480324] [<8055f938>] do_execve+0x38/0x44 [ 14.485137] [<80413808>] handle_sys+0x128/0x14c These code paths write into a page, call flush_dcache_page then call set_pte_at without flush_icache_page inbetween. The end result is that the icache can become corrupted & userland processes may execute unexpected or invalid code, typically resulting in a reserved instruction exception, a trap or a segfault. Fix this race condition fully by performing any cache maintenance required to keep the icache & dcache in sync in set_pte_at, before the page is made valid. This has the added bonus of ensuring the cache maintenance always happens in one location, rather than being duplicated in flush_icache_page & update_mmu_cache. It also matches the way other architectures solve the same problem (see arm, ia64 & powerpc). Signed-off-by:Ionela Voinescu <ionela.voinescu@imgtec.com> Cc: Lars Persson <lars.persson@axis.com> Fixes: 4d46a67a ("MIPS: Fix race condition in lazy cache flushing.") Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: David Daney <david.daney@cavium.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Jerome Marchand <jmarchan@redhat.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable <stable@vger.kernel.org> # v4.1+ Patchwork: https://patchwork.linux-mips.org/patch/12722/Signed-off-by:
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Paul Burton authored
The following patch will expose __update_cache to highmem pages. Handle them by mapping them in for the duration of the cache maintenance, just like in __flush_dcache_page. The code for that isn't shared because we need the page address in __update_cache so sharing became messy. Given that the entirity is an extra 5 lines, just duplicate it. Signed-off-by:
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Paul Burton authored
When flush_dcache_page is called on an executable page, that page is about to be provided to userland & we can presume that the icache contains no valid entries for its address range. However if the icache does not fill from the dcache then we cannot presume that the pages content has been written back as far as the memories that the dcache will fill from (ie. L2 or further out). This was being done for lowmem pages, but not for highmem which can lead to icache corruption. Fix this by mapping highmem pages & flushing their content from the dcache in __flush_dcache_page before providing the page to userland, just as is done for lowmem pages. Signed-off-by:
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Paul Burton authored
The flush_kernel_dcache_page function was previously essentially a nop. This is incorrect for MIPS, where if a page has been modified & either it aliases or it's executable & the icache doesn't fill from dcache then the content needs to be written back from dcache to the next level of the cache hierarchy (which is shared with the icache). Implement this by simply calling flush_dcache_page, treating this kmapped cache flush function (flush_kernel_dcache_page) exactly the same as its non-kmapped counterpart (flush_dcache_page). Signed-off-by:
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Aaro Koskinen authored
Some drivers for SoC provided functionality are missing. Enable to those in defconfig to provide better build/testing coverage. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12750/Signed-off-by:
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Zubair Lutfullah Kakakhel authored
DSPv3 is supported on all MIPSr6 systems which indicate support for DSPv2. This doesn't require any changes to the kernel's handling of DSP resources. The patch is to detect support and indicate it in /proc/cpuinfo DSP v3 introduces a new instruction BPOSGE32C Signed-off-by:
Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by:
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Andrei Pistirica authored
This adds UART and a serial console driver for Microchip PIC32 class devices. [ralf@linux-mips.org: Resolved merge conflict.] Signed-off-by:
Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by:
Joshua Henderson <joshua.henderson@microchip.com> Reviewed-by:
Alan Cox <alan@linux.intel.com> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org Cc: linux-api@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12101/Signed-off-by:
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Andrei Pistirica authored
Document the devicetree bindings for the UART peripheral found on Microchip PIC32 class devices. Signed-off-by:
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James Hogan authored
The MIPS_CPU_* definitions have now filled the first 32-bits, and are getting longer since they're written in hex without zero padding. Adding my 8 extra MIPS_CPU_* definitions which I haven't upstreamed yet this is getting increasingly ugly as the comments get shifted progressively to the right. Its also error prone, and I've seen this cause mistakes on 3 separate occasions now, not helped by it being a conflict hotspot. Convert all the MIPS_CPU_* definitions to the form (1ull << x). Humans are better at incrementing than shifting. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10045/Signed-off-by:
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James Hogan authored
The MIPS_CPU_* definitions accidentally missed bits 27..30 when MIPS_CPU_EVA was added, and further definitions have continued from there. Shift all the definitions since MIPS_CPU_EVA right by 4 so there are no gaps. Signed-off-by:
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Florian Fainelli authored
Port the stblinux-3.3 code to perform a bunch of CPU-specific initialization, make it compatible with run-time detection of the CPU, and unroll the brcmstb-specific macros: BDEV_RB(), BDEV_UNSET. The "pref 30" disabling is done as a quirk. This is a preliminary change to allow the use of the "rotr" instruction gated by cpu_has_rixi. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12504/Signed-off-by:
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Maciej W. Rozycki authored
Avoid a reader's confusion, as the calculation is correct either way. Signed-off-by:
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Florian Fainelli authored
MIPS kernels allow platforms to invoke a custom Bus Error handler, add the necessary code to do this for Broadcom SoCs where the GISB bus error handler can be used. We may get a bus error from an address decoded outside of the GISB bus space, so we need to check the validity of such a capture before printing anything. Signed-off-by:
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Zubair Lutfullah Kakakhel authored
Add basic CN7XXX interface detection. This allows the kernel to boot with ethernet working as it initializes the ethernet ports with SGMII instead of defaulting to RGMII routines. Tested on the utm8 from Rhino Labs with a CN7130. Signed-off-by:
David Daney <david.daney@cavium.com> Cc: janne.huttunen@nokia.com Cc: aaro.koskinen@nokia.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12376/Signed-off-by:
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Ralf Baechle authored
Avoids function calls to an empty function. Signed-off-by: -
Paul Burton authored
MIPS32 code uses rel-style relocs, and MIPS32r6 modules may include R_MIPS_PC16, R_MIPS_PC21 & R_MIPS_PC26 relocations. We thus need to support these relocations in order to load MIPS32r6 kernel modules. This patch adds such support, which is similar to the rela-style support in module-rela.c but making use of the implicit addend from the instruction encoding. Signed-off-by:
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Paul Burton authored
MIPS64 code uses rela-style relocs, and MIPS64r6 modules may include the new R_MIPS_PC21 & R_MIPS_PC26 relocations. We thus need to support these relocations in order to load MIPS64r6 kernel modules. They are similar to the existing R_MIPS_PC16 relocation but applying to a wider field. Implement support for them by genericising the existing R_MIPS_PC16 implementation such that it can be used for different field widths, and calling it for all 3 reloc types. Signed-off-by:
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Steven J. Hill authored
The module relocation handling code has inconsistent use of printk() and pr_*() functions. Convert printk() calls to use pr_err() and pr_warn(). [paul.burton@imgtec.com: Do the same thing in module.c] Signed-off-by:
Steven J. Hill <sjhill@realitydiluted.com> Signed-off-by:
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Paul Burton authored
Support probing the M6250 CPU now that cases for handling it have been added where required in the core MIPS kernel code. Signed-off-by:
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Paul Burton authored
Add casses supporting the M6250 CPU to various switch statements in the core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by:
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Paul Burton authored
Define the processor ID for the M6250 CPU and add a value to the enum cpu_type_enum for the core. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
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Paul Burton authored
Support probing the P6600 core now that cases for handling it have been added throughout the core MIPS kernel code. Signed-off-by:
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Paul Burton authored
Add cases supporting the P6600 CPU to various switch statements in core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by:
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Paul Burton authored
Define the processor ID for the P6600 core and add a value to the enum cpu_type_enum for the core. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
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Ralf Baechle authored
Signed-off-by: -
Paul Burton authored
There are CPUs/bitfiles available for use with SEAD3 boards which implement release 6 of the MIPS architecture. Allow building the kernel for such a system. Signed-off-by:
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Paul Burton authored
When CONFIG_MIPS_CPS_NS16550 is enabled, some register state is dumped to the UART when an exception is taken via the BEV on secondary cores. EJTAG exceptions are architecturally expected to be handled by the BEV even when Status.BEV is 0. This effectively means that if userland executes an sdbbp instruction on a secondary core then the kernel dumps register state to the UART even though the exception is perfectly normal & expected. Prevent this by simply not dumping information to the UART for EJTAG exceptions. Fixes: 609cf6f2 ("MIPS: CPS: Early debug using an ns16550-compatible UART") Signed-off-by:
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Paul Burton authored
When debugging a new system or core it can be useful to disable the use of multithreading. Introduce a "nothreads" kernel command line parameter that can be set in order to do so. Signed-off-by:
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