- 22 Feb, 2011 1 commit
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Colin Cross authored
Some peripheral clocks share enable bits. Refcount the enables so that calling clk_disable on one clock will not turn off another clock. Signed-off-by:
Colin Cross <ccross@android.com> Acked-by:
Olof Johansson <olof@lixom.net>
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- 21 Feb, 2011 20 commits
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Colin Cross authored
Correct max rates for pclk and sclk (Originally fixed by Dima Zavin <dima@android.com>) Correct max rate for plla (Originally fixed by Stephen Warren <swarren@nvidia.com>) Remove unnecessary no-op set_rate on audio clocks Add clock lookup entries for grhost, bsea, and vde clocks Update clock clookup entries for vcp, bsea, and vde clocks Add shared clock entries for sclk and emc Add a virtual cop clock to provide a reset op (Originally fixed by Dima Zavin <dima@android.com>) Pass set_rate on super clocks through to parent Fix pllx frequency table entry for 608 MHz Remove incorrect plla frequency table entries Acked-by:
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Colin Cross authored
The PLLP registers are now being restored by the low-level resume code, and the CPU may be running off PLLP, so don't touch them during clock resume. Save plld, plls, pllu, and audio clock during suspend (originally fixed by Mayuresh Kulkarni <mkulkarni@nvidia.com>) The lock time for plld is 1000 us, so increase the delay after setting the PLLs. Add a BUG_ON to ensure the size of the suspend context area is correct. Acked-by:
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Colin Cross authored
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by:
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Colin Cross authored
Adjusts the minimum memory frequency when the cpu frequency changes. The values are currently hardcoded to a reasonable default. If memory frequency scaling is not enabled this patch will have no effect. Acked-by:
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Colin Cross authored
Add clock ops on the emc peripheral clock that call into the emc driver to update the memory controller registers for the new frequency. Tegra has an interlock between the clock controller and the memory controller that prevents the new register values from taking effect until the clock frequency update occurs. Acked-by:
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Colin Cross authored
The frequency memory bus on Tegra can be adjusted without disabling accesses to memory by updating the memory configuration registers from a per-board table, and then changing the clock frequency. The clock controller and memory controller have an interlock that prevents the new memory registers from taking effect until the clock frequency change. Acked-by:
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Colin Cross authored
Remove unnecessary uses of #ifdef CONFIG_DEBUG_FS Convert bool assignments from 1 to true Acked-by:
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Colin Cross authored
Some clocks may have multiple downstream users that need to request a higher clock rate. Shared bus clocks provide a unique shared_bus_user clock to each user. The frequency of the bus is set to the highest enabled shared_bus_user clock, with a minimum value set by the shared bus. Drivers can use clk_enable and clk_disable to enable or disable their requirement, and clk_set_rate to set the minimum rate. Acked-by:
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Colin Cross authored
During cpu frequency changes, take an extra reference to pllx so that it doesn't turn off and on while the cpu is temporarily on pllp. If the cpu is moved to pllp permanently, pllx will be turned off. Acked-by:
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Colin Cross authored
Give each clock its own lock, and remove all lock traversals from parent to child clocks to prevent AB-BA deadlocks. This brings the locking in line with the common struct clk patches and should make conversion simple. Acked-by:
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Colin Cross authored
Creates a union of a struct for each type of clock to reduce memory usage and clarify which members are used by all clocks and which are used by a single type. Acked-by:
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Colin Cross authored
Make the static clocks look more like the array of clocks so they can all be initalized with the same helper function. Acked-by:
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Colin Cross authored
The existing version did not extend well to core dvfs, drop it for now until the new clk api with clk_prepare and clk_unprepare is ready and non-atomic clocks are possible. Acked-by:
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Colin Cross authored
Assume that any clock that has no enable op is always on. Acked-by:
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Colin Cross authored
The PLL lock bits are not reliable, use per-PLL timeouts instead. Acked-by:
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Colin Cross authored
Drop the unnecessary pr_debug calls to avoid having to maintain them. Acked-by:
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Colin Cross authored
When updating the CPU PLL frequency, keeping the PLL enabled avoids ramping the PLL all the way down and back up again. Remove the BUG_ON in tegra2_pll_clk_set_rate to allow the rate to change while the PLL is enabled. Acked-by:
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Dima Zavin authored
Add a new 'reset' clk op. This can be provided for any clock, not just peripherals. Signed-off-by:
Dima Zavin <dima@android.com> Acked-by:
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Simon Glass authored
This seems to be a regression in 2.6.37. We cannot use writel() here since the resulting wmb() calls l2x0_cache_sync() which uses a spinlock and L1 cache may be off at this point. http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041909.htmlSigned-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
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Stephen Warren authored
Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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- 19 Feb, 2011 2 commits
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Stephen Warren authored
If a request already in the queue is passed to tegra_dma_enqueue_req, tegra_dma_req.node->{next,prev} will end up pointing to itself instead of at tegra_dma_channel.list, which is the way a the end-of-list should be set up. When the DMA request completes and is list_del'd, the list head will still point at it, yet the node's next/prev will contain the list poison values. When the next DMA request completes, a kernel panic will occur when those poison values are dereferenced. This makes the DMA driver more robust in the face of buggy clients. Signed-off-by: -
Colin Cross authored
Merge branch 'tegra-arch' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6 into outside-for-next
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- 11 Feb, 2011 7 commits
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Mike Rapoport authored
Add basic support for CompuLab TrimSlice platform Signed-off-by:
Mike Rapoport <mike@compulab.co.il> Signed-off-by:
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Colin Cross authored
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Olof Johansson authored
Adding one single defconfig for the tegra family of boards, to over time cover the superset of supported platform and drivers. Signed-off-by:
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Colin Cross authored
Sometimes, due to high interrupt latency in the continuous mode of DMA transfer, the half buffer complete interrupt is handled after DMA has transferred the full buffer. When this is detected, stop DMA immediately and restart with the next buffer if the next buffer is ready. originally fixed by Victor(Weiguo) Pan <wpan@nvidia.com> In place of using the simple spin_lock()/spi_unlock() in the interrupt thread, using the spin_lock_irqsave() and spin_unlock_irqrestore(). The lock is shared between the normal process context and interrupt context. originally fixed by Laxman Dewangan (ldewangan@nvidia.com) The use of shadow registers caused memory corruption at physical address 0 because the enable bit was not shadowed, and assuming it needed to be set would enable an unconfigured dma block. Most of the register accesses don't need to know the previous state of the registers, and the few places that do need to modify only a few bits in the registers are the same ones that were sometimes incorrectly setting the enable bit. This patch convert tegra_dma_update_hardware to set the entire register, and the other users to read-modify-write, and drops the shadow registers completely. Also fixes missing locking in tegra_dma_allocate_channel Signed-off-by: -
Colin Cross authored
Signed-off-by: -
Colin Cross authored
On Tegra, calling clk_set_rate on the CPU clock may call into the regulator API. If the regulator driver that controls the CPU voltage rail has been suspended, this can lead to attempted communication with a hardware block that has already been turned off. Adds a SUSPEND_PREPARE notification hook to drop the frequency to the lowest possible during suspend. Also adds 216MHz (off of PLLP) as the lowest CPU frequency, which allows PLLX to be turned off. Signed-off-by: -
Gary King authored
Adds gart, hdmi, avp, host1x, and pwm controllers to mach/iomap.h Signed-off-by:
Gary King <gking@nvidia.com> Signed-off-by:
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- 10 Feb, 2011 9 commits
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Colin Cross authored
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Colin Cross authored
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Colin Cross authored
Implement read_persistent_clock by reading the Tegra RTC registers that stay running during suspend. Save and restore the timer configuration register in suspend. Signed-off-by: -
Gary King authored
Adds missing drive pingroups, saves all drive pingroups in suspend, and restores the pinmux registers in the proper order. Signed-off-by:
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Colin Cross authored
Save and restore pll and osc state during suspend Add digital audio clocks Update clk dev associations Correct max clock frequencies Add pll_p as additional cpu clock state Add values to plld table Fix register offset for sdmmc4 clock Add blink timer to tegra2_clocks Signed-off-by: -
Colin Cross authored
Signed-off-by: -
Colin Cross authored
Fixes typo in INT_CPU1_PMU_INTR (original fix from Will Deacon) Adds board irqs Signed-off-by: -
Colin Cross authored
Signed-off-by: -
Colin Cross authored
Signed-off-by:
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- 08 Feb, 2011 1 commit
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Linus Torvalds authored
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