1. 19 Jan, 2018 1 commit
    • Michael Ellerman's avatar
      powerpc/64s: Fix ps3 build error due to tlbiel_all() · 7a074fc0
      Michael Ellerman authored
      The recent changes to TLB handling broke the PS3 build:
      
        arch/powerpc/include/asm/book3s/64/tlbflush.h:30: undefined reference to `.hash__tlbiel_all'
      
      Fix it by adding an fallback version of tlbiel_all() for non-native
      builds. It should never be called, due to checks in callers so it
      calls BUG(). We should probably clean it up further but this will
      suffice for now.
      
      Fixes: d4748276 ("powerpc/64s: Improve local TLB flush for boot and MCE on POWER9")
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      7a074fc0
  2. 18 Jan, 2018 6 commits
  3. 17 Jan, 2018 7 commits
    • Nicholas Piggin's avatar
      powerpc/pseries: lift RTAS limit for hash · c610d65c
      Nicholas Piggin authored
      With the previous patch to switch to 64-bit mode after returning from
      RTAS and before doing any memory accesses, the RMA limit need not be
      clamped to 1GB to avoid RTAS bugs.
      
      Keep the 1GB limit for older firmware (although this is more of a kernel
      concern than RTAS), and remove it starting with POWER9.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      c610d65c
    • Nicholas Piggin's avatar
      powerpc/pseries: lift RTAS limit for radix · 5eae82ca
      Nicholas Piggin authored
      With the previous patch to switch to 64-bit mode after returning from
      RTAS and before doing any memory accesses, the RMA limit need not be
      clamped to 1GB to avoid RTAS bugs.
      
      Keep the 1GB limit for older firmware (although this is more of a kernel
      concern than RTAS), and remove it starting with POWER9.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      5eae82ca
    • Nicholas Piggin's avatar
      powerpc/64: rtas avoid accessing paca in 32-bit mode · 47fee31d
      Nicholas Piggin authored
      Commit 177ba7c6 ("powerpc/mm/radix: Limit paca allocation in radix")
      limited the paca allocation address to 1G on pSeries because RTAS return
      accesses the paca in 32-bit mode:
      
          On return from RTAS we access the paca variables and we have 64 bit
          disabled. This requires us to limit paca in 32 bit range.
      
          Fix this by setting ppc64_rma_size to first_memblock_size/1G range.
      
      Avoid this limit by switching to 64-bit mode before accessing any memory.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      47fee31d
    • Nicholas Piggin's avatar
      powerpc/pseries: radix is not subject to RMA limit, remove it · 98ae0069
      Nicholas Piggin authored
      The radix guest is not subject to the paravirtualized HPT VRMA limit,
      so remove that from ppc64_rma_size calculation for that platform.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      98ae0069
    • Nicholas Piggin's avatar
      powerpc/powernv: Remove real mode access limit for early allocations · 1513c33d
      Nicholas Piggin authored
      This removes the RMA limit on powernv platform, which constrains
      early allocations such as PACAs and stacks. There are still other
      restrictions that must be followed, such as bolted SLB limits, but
      real mode addressing has no constraints.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      1513c33d
    • Nicholas Piggin's avatar
      powerpc/64s: Improve local TLB flush for boot and MCE on POWER9 · d4748276
      Nicholas Piggin authored
      There are several cases outside the normal address space management
      where a CPU's entire local TLB is to be flushed:
      
        1. Booting the kernel, in case something has left stale entries in
           the TLB (e.g., kexec).
      
        2. Machine check, to clean corrupted TLB entries.
      
      One other place where the TLB is flushed, is waking from deep idle
      states. The flush is a side-effect of calling ->cpu_restore with the
      intention of re-setting various SPRs. The flush itself is unnecessary
      because in the first case, the TLB should not acquire new corrupted
      TLB entries as part of sleep/wake (though they may be lost).
      
      This type of TLB flush is coded inflexibly, several times for each CPU
      type, and they have a number of problems with ISA v3.0B:
      
      - The current radix mode of the MMU is not taken into account, it is
        always done as a hash flushn For IS=2 (LPID-matching flush from host)
        and IS=3 with HV=0 (guest kernel flush), tlbie(l) is undefined if
        the R field does not match the current radix mode.
      
      - ISA v3.0B hash must flush the partition and process table caches as
        well.
      
      - ISA v3.0B radix must flush partition and process scoped translations,
        partition and process table caches, and also the page walk cache.
      
      So consolidate the flushing code and implement it in C and inline asm
      under the mm/ directory with the rest of the flush code. Add ISA v3.0B
      cases for radix and hash, and use the radix flush in radix environment.
      
      Provide a way for IS=2 (LPID flush) to specify the radix mode of the
      partition. Have KVM pass in the radix mode of the guest.
      
      Take out the flushes from early cputable/dt_cpu_ftrs detection hooks,
      and move it later in the boot process after, the MMU registers are set
      up and before relocation is first turned on.
      
      The TLB flush is no longer called when restoring from deep idle states.
      This was not be done as a separate step because booting secondaries
      uses the same cpu_restore as idle restore, which needs the TLB flush.
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      d4748276
    • Nicholas Piggin's avatar
      powerpc: System reset avoid interleaving oops using die synchronisation · 4552d128
      Nicholas Piggin authored
      The die() oops path contains a serializing lock to prevent oops
      messages from being interleaved. In the case of a system reset
      initiated oops (e.g., qemu nmi command), __die was being called
      which lacks that synchronisation and oops reports could be
      interleaved across CPUs.
      
      A recent patch 4388c9b3 ("powerpc: Do not send system reset
      request through the oops path") changed this to __die to avoid
      the debugger() call, but there is no real harm to calling it twice
      if the first time fell through. So go back to using die() here.
      This was observed to fix the problem.
      
      Fixes: 4388c9b3 ("powerpc: Do not send system reset request through the oops path")
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      4552d128
  4. 16 Jan, 2018 26 commits