- 19 Oct, 2017 27 commits
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Christian König authored
And return from the wait functions the fence error code. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Instead of per device track the VRAM lost per context and return ECANCELED instead of ENODEV. Signed-off-by:
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Christian König authored
Instead of reading the current counter from fpriv. Signed-off-by:
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Christian König authored
Keep blocking the CS, but revert everything else. Mapping BOs and info IOCTL are harmless and can still happen even when VRAM content ist lost. Signed-off-by:
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Christian König authored
Add a new huge page pool and try to allocate from it when it makes sense. v2: avoid compound pages for now Signed-off-by:
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Christian König authored
Make it easier to add huge page pool. Signed-off-by:
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Christian König authored
Try to allocate huge pages when it makes sense. v2: avoid compound pages for now Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
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Christian König authored
We need to figure out first how to correctly map them into the CPU page tables. bug: https://bugs.freedesktop.org/show_bug.cgi?id=103138Signed-off-by:
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Ken Wang authored
Old value from bringup was wrong. Cc: stable@vger.kernel.org Signed-off-by:
Ken Wang <Ken.Wang@amd.com> Reviewed-by:
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Horace Chen authored
SR-IOV need to exchange some data between PF&VF through shared VRAM PF will copy some necessary firmware and information to the shared VRAM. It also requires some information from VF. PF will send a key through mailbox2 to help guest calculate checksum so that it can verify whether the data is correct. So check the data on the specified offset of the shared VRAM, if the checksum is right, read values from it and write some VF information next to the data from PF. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Helps avoiding deadlock during GPU reset. Added mutex to amdgpu_ctx to preserve order of fences on a ring. v2: Put waiting logic in a function in a seperate function in amdgpu_ctx.c Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
This enables old fence waiting before reservation lock is aquired which in turn is part of a bigger solution to deadlock happening when gpu reset with VRAM recovery accures during intensive rendering. Signed-off-by:
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Colin Ian King authored
The function uvd_v6_0_enc_get_destroy_msg is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'uvd_v6_0_enc_get_destroy_msg' was not declared. Should it be static? Reviewed-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Rex Zhu authored
move functions in polaris_smc.c to polaris10_smumgr.c and make all functions in polaris10_smumgr.c static. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
move functions in tonga_smc.c to tonga_smumgr.c and make all functions in tonga_smumgr.c static. Reviewed-by:
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Rex Zhu authored
move functions in iceland_smc.c to iceland_smumgr.c and make all functions in iceland_smumgr.c static. Reviewed-by:
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Rex Zhu authored
make all functions in fiji_smumgr.c static and exported by pp_smumgr_func table. Reviewed-by:
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Rex Zhu authored
for consistency. Reviewed-by:
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Rex Zhu authored
in function amdgpu_ucode_init_bo, when failed, it will set load_type to AMDGPU_FW_LOAD_DIRECT. Reviewed-by:
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Rex Zhu authored
fiji and polaris can share same setup_pwr_virus function. Reviewed-by:
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Rex Zhu authored
Used for smu power logging. Reviewed-by:
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Rex Zhu authored
Used for smu power logging. Reviewed-by:
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Rex Zhu authored
used for notify SMU the allocated buffer address. Reviewed-by:
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Rex Zhu authored
New messages for smu power logging. Reviewed-by:
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Satyajit Sahu authored
Setting the function pointer to the get the temperature on CZ. Reviewed-by:
Satyajit Sahu <satyajit.sahu@amd.com> Signed-off-by:
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Alex Deucher authored
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Andres Rodriguez authored
Don't leak implementation details about how each priority behaves to usermode. This allows greater flexibility in the future. Squash into c2636dc5Signed-off-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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- 09 Oct, 2017 13 commits
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Andres Rodriguez authored
The AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE ioctls are used to set the priority of a different process in the current system. When a request is dropped, the process's contexts will be restored to the priority specified at context creation time. A request can be dropped by setting the override priority to AMDGPU_CTX_PRIORITY_UNSET. An fd is used to identify the remote process. This is simpler than passing a pid number, which is vulnerable to re-use, etc. This functionality is limited to DRM_MASTER since abuse of this interface can have a negative impact on the system's performance. v2: removed unused output structure v3: change refcounted interface for a regular set operation Signed-off-by:
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Andres Rodriguez authored
Introduce amdgpu_ctx_priority_override(). A mechanism to override a context's priority. An override can be terminated by setting the override to AMD_SCHED_PRIORITY_UNSET. v2: change refcounted interface for a direct set Signed-off-by:
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Andres Rodriguez authored
Use _INVALID to identify bad parameters and _UNSET to represent the lack of interest in a specific value. Signed-off-by:
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Andres Rodriguez authored
This is useful for changing an entity's priority at runtime. v2: don't modify the order of amd_sched_entity members Reviewed-by:
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Andres Rodriguez authored
Returning invalid priorities as _NORMAL is a backwards compatibility quirk of amdgpu_ctx_ioctl(). Move this detail one layer up where it belongs. Signed-off-by:
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Andres Rodriguez authored
Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over other queues on the same pipe. Multiple queues on a pipe are timesliced so this gives us full precedence over other queues. Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the wave as follows: 0x2: CS_H 0x1: CS_M 0x0: CS_L The SPI block will then dispatch work according to the policy set by SPI_ARB_PRIORITY. In the current policy CS_H is higher priority than gfx. In order to prevent getting stuck in loops of resources bouncing between GFX and high priority compute and introducing further latency, we statically reserve a portion of the pipe. v2: fix srbm_select to ring->queue and use ring->funcs->type v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_* v4: switch int to enum amd_sched_priority v5: corresponding changes for srbm_lock v6: change CU reservation to PIPE_PERCENT allocation v7: use kiq instead of MMIO v8: back to MMIO, and make the implementation sleep safe. v9: corresponding changes for splitting HIGH into _HW/_SW Acked-by: -
Andres Rodriguez authored
Add an initial framework for changing the HW priorities of rings. The framework allows requesting priority changes for the lifetime of an amdgpu_job. After the job completes the priority will decay to the next lowest priority for which a request is still valid. A new ring function set_priority() can now be populated to take care of the HW specific programming sequence for priority changes. v2: set priority before emitting IB, and take a ref on amdgpu_job v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_* v4: plug amdgpu_ring_restore_priority_cb into amdgpu_job_free_cb v5: use atomic for tracking job priorities instead of last_job v6: rename amdgpu_ring_priority_[get/put]() and align parameters v7: replace spinlocks with mutexes for KIQ compatibility v8: raise ring priority during cs_ioctl, instead of job_run v9: priority_get() before push_job() Reviewed-by:
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Andres Rodriguez authored
Add a new context creation parameter to express a global context priority. The priority ranking in descending order is as follows: * AMDGPU_CTX_PRIORITY_HIGH_HW * AMDGPU_CTX_PRIORITY_HIGH_SW * AMDGPU_CTX_PRIORITY_NORMAL * AMDGPU_CTX_PRIORITY_LOW_SW * AMDGPU_CTX_PRIORITY_LOW_HW The driver will attempt to schedule work to the hardware according to the priorities. No latency or throughput guarantees are provided by this patch. This interface intends to service the EGL_IMG_context_priority extension, and vulkan equivalents. Setting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER. v2: Instead of using flags, repurpose __pad v3: Swap enum values of _NORMAL _HIGH for backwards compatibility v4: Validate usermode priority and store it v5: Move priority validation into amdgpu_ctx_ioctl(), headline reword v6: add UAPI note regarding priorities requiring CAP_SYS_ADMIN v7: remove ctx->priority v8: added AMDGPU_CTX_PRIORITY_LOW, s/CAP_SYS_ADMIN/CAP_SYS_NICE v9: change the priority parameter to __s32 v10: split priorities into _SW and _HW v11: Allow DRM_MASTER without CAP_SYS_NICE Reviewed-by:
Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by:
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Andres Rodriguez authored
Introduce a flag to signal that access to a BO will be synchronized through an external mechanism. Currently all buffers shared between contexts are subject to implicit synchronization. However, this is only required for protocols that currently don't support an explicit synchronization mechanism (DRI2/3). This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that users can specify when it is safe to disable implicit sync. v2: only disable explicit sync in amdgpu_cs_ioctl Reviewed-by:
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Andres Rodriguez authored
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Christian König authored
Convert GTT mappings into linear ones for huge page handling. v2: use fragment size as minimum for linear conversion Signed-off-by:
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Christian König authored
Instead of mapping them bit by bit map/unmap all consecutive pages as in one call. v2: test for consecutive pages instead of using compound page order. Signed-off-by:
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Christian König authored
Totally surprisingly this is more efficient than doing it page by page. Signed-off-by:
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