1. 06 Jul, 2015 7 commits
  2. 02 Jul, 2015 4 commits
  3. 22 Jun, 2015 2 commits
  4. 20 Jun, 2015 7 commits
    • Michael Turquette's avatar
      Merge tag 'tegra-for-4.2-clk' of... · 2cd7b043
      Michael Turquette authored
      Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
      
      clk: tegra: Changes for v4.2-rc1
      
      This contains the EMC clock driver that's been exhaustively reviewed and
      tested. It also includes a change to the clock core that allows a clock
      provider to perform low-level reparenting of clocks. This is required by
      the EMC clock driver because the reparenting needs to be done at a very
      specific point in time during the EMC frequency switch.
      2cd7b043
    • Michael Turquette's avatar
      Merge branch 'clk-exynos-cpu-clk' into clk-next · 85e88fab
      Michael Turquette authored
      Folded into this merge commit is a build error fix: s/clk/core in
      clk_change_rate due to the new struct clk_core
      85e88fab
    • Thomas Abraham's avatar
      cpufreq: exynos: remove Exynos4210 specific cpufreq driver support · 8eb92ab6
      Thomas Abraham authored
      Exynos4210 based platforms have switched over to use generic
      cpufreq driver for cpufreq functionality. So the Exynos
      specific cpufreq support for these platforms can be removed.
      
      Changes by Bartlomiej:
      - dropped Exynos5250 support removal for now
      - updated exynos-cpufreq.[c,h]
      
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      8eb92ab6
    • Thomas Abraham's avatar
      ARM: Exynos: switch to using generic cpufreq driver for Exynos4210 · 131323cd
      Thomas Abraham authored
      The new CPU clock type allows the use of generic CPUfreq driver.
      Switch Exynos4210 to using generic cpufreq driver.
      
      Changes by Bartlomiej:
      - removed non-Exynos4210 support for now
      
      Cc: Tomasz Figa <tomasz.figa@gmail.com>
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      131323cd
    • Thomas Abraham's avatar
      clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock · 6ae5a0b4
      Thomas Abraham authored
      With the addition of the new Samsung specific cpu-clock type, the
      arm clock can be represented as a cpu-clock type. Add the CPU clock
      configuration data and instantiate the CPU clock type for Exynos4210.
      
      Changes by Bartlomiej:
      - fixed issue with wrong dividers being setup by Common Clock Framework
        (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock,
        without this change cpufreq-dt driver showed ~10 mA larger energy
        consumption when compared to cpufreq-exynos one when "performance"
        cpufreq governor was used on Exynos4210 SoC based Origen board), this
        was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE
        and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in
        "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update
        clock flags") but using these flags is not sufficient to fix the issue
        observed
      - removed Exynos5250 and Exynos5420 support for now
      
      Cc: Tomasz Figa <tomasz.figa@gmail.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      6ae5a0b4
    • Thomas Abraham's avatar
      clk: samsung: add infrastructure to register cpu clocks · ddeac8d9
      Thomas Abraham authored
      The CPU clock provider supplies the clock to the CPU clock domain. The
      composition and organization of the CPU clock provider could vary among
      Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
      and gates. This patch defines a new clock type for CPU clock provider and
      adds infrastructure to register the CPU clock providers for Samsung
      platforms.
      
      Changes by Bartlomiej:
      - fixed issue with setting lower dividers before the parent clock speed
        was lowered (the issue resulted in lockup on Exynos4210 SoC based
        Origen board when "ondemand" cpufreq governor was stress tested)
      - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
        problem by moving cfg_data search outside of the spin locked area
      - removed leftover kfree() in exynos_register_cpu_clock() that could
        result in dereferencing the NULL pointer on error
      - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
        reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
      - added missing "last chance" checks to wait_until_divider_stable() and
        wait_until_mux_stable() (needed in case that IRQ handling took long
        time to proceed and resulted in function printing incorrect error
        message about timeout)
      - moved E4210_CPU_DIV[0,1]() macros just before their only users,
        this resulted in moving them from patch #2 to patch #3/6 ("clk:
        samsung: exynos4: add cpu clock configuration data and instantiate
        cpu clock")
      - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
        macros for now
      - added my Copyrights to drivers/clk/samsung/clk-cpu.c
      
      Cc: Tomasz Figa <tomasz.figa@gmail.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      ddeac8d9
    • Bartlomiej Zolnierkiewicz's avatar
      clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support · d8d91987
      Bartlomiej Zolnierkiewicz authored
      This flag is needed to fix the issue with wrong dividers being setup
      by Common Clock Framework when using the new Exynos cpu clock support.
      
      The issue happens because clk_core_set_rate_nolock()  calls
      clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
      a chance to run.  In case of Exynos cpu clock support pre/post clock
      notifiers are registered for mout_apll clock which is a parent of armclk
      cpu clock and dividers are modified in both pre and post clock notifier.
      This results in wrong dividers values being later programmed by
      clk_change_rate(top).  To workaround the problem CLK_RECALC_NEW_RATES
      flag is added and it is set for mout_apll clock later so the correct
      divider values are re-calculated after both pre and post clock notifiers
      had run.
      
      For example when using "performance" governor on Exynos4210 Origen board
      the cpufreq-dt driver requests to change the frequency from 1000MHz to
      1200MHz and after the change state of the relevant clocks is following:
      
      Without use of CLK_GET_RATE_NOCACHE flag:
      
       fout_apll rate: 1200000000
               fout_apll_div_2 rate: 600000000
                       mout_clkout_cpu rate: 600000000
                               div_clkout_cpu rate: 600000000
                                       clkout_cpu rate: 600000000
               mout_apll rate: 1200000000
                       armclk rate: 1200000000
                       mout_hpm rate: 1200000000
                               div_copy rate: 300000000
                                       div_hpm rate: 300000000
                       mout_core rate: 1200000000
                               div_core rate: 1200000000
                                       div_core2 rate: 1200000000
                                               arm_clk_div_2 rate: 600000000
                                               div_corem0 rate: 300000000
                                               div_corem1 rate: 150000000
                                               div_periph rate: 300000000
                               div_atb rate: 300000000
                                       div_pclk_dbg rate: 150000000
                       sclk_apll rate: 1200000000
                               sclk_apll_div_2 rate: 600000000
      
      With use of CLK_GET_RATE_NOCACHE flag:
      
       fout_apll rate: 1200000000
               fout_apll_div_2 rate: 600000000
                       mout_clkout_cpu rate: 600000000
                               div_clkout_cpu rate: 600000000
                                       clkout_cpu rate: 600000000
               mout_apll rate: 1200000000
                       armclk rate: 1200000000
                       mout_hpm rate: 1200000000
                               div_copy rate: 200000000
                                       div_hpm rate: 200000000
                       mout_core rate: 1200000000
                               div_core rate: 1200000000
                                       div_core2 rate: 1200000000
                                               arm_clk_div_2 rate: 600000000
                                               div_corem0 rate: 300000000
                                               div_corem1 rate: 150000000
                                               div_periph rate: 300000000
                               div_atb rate: 240000000
                                       div_pclk_dbg rate: 120000000
                       sclk_apll rate: 150000000
                               sclk_apll_div_2 rate: 75000000
      
      Without this change cpufreq-dt driver showed ~10 mA larger energy
      consumption when compared to cpufreq-exynos one when "performance"
      cpufreq governor was used on Exynos4210 SoC based Origen board.
      
      This issue was probably meant to be workarounded by use of
      CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
      the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
      samsung: remove unused clock aliases and update clock flags" patch)
      but usage of these flags is not sufficient to fix the issue observed.
      
      Cc: Thomas Abraham <thomas.ab@samsung.com>
      Cc: Tomasz Figa <tomasz.figa@gmail.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      d8d91987
  5. 18 Jun, 2015 12 commits
  6. 17 Jun, 2015 3 commits
  7. 12 Jun, 2015 2 commits
  8. 10 Jun, 2015 3 commits