- 31 May, 2018 3 commits
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Shaoyun Liu authored
When PP block is disabled, return a fix value(100M) for mclk and sclk on bare-metal mode. This will cover the emulation mode as well. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Feifei Xu authored
Update mmCB_DCC_CONFIG register goldensetting. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Rex Zhu authored
if max od engine clock limit and memory clock limit are not set in vbios. driver will allow underclocking instand of disable od feature completely. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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- 30 May, 2018 7 commits
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Alex Deucher authored
Fixes a crash on asics without powerplay yet (e.g., vega20). Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: -
Mikita Lipski authored
Get rid of an empty dublicate of smu10_display_clock_voltage_request Add display_clock_voltage_request to smu10 functions struct so it can be called from outside the class and connect the pointer to the function. That way Display driver can finally apply clock voltage requests when needed. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Evan Quan authored
The AMD_CG_SUPPORT_HDP_LS was wrongly written as AMD_CG_SUPPORT_BIF_LS. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Evan Quan authored
The .syspll_id and .dfsdid are not initialzed correctly. And le32_to_cpu transfer is needed on the output. Signed-off-by:
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Evan Quan authored
The SMU11 SYSPLL0 clock ids were assigned wrong values. Signed-off-by:
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Chunming Zhou authored
In per-vm-bo case, there could be no bo list. But gds bo created from user space must be passed to bo list. So adding a check to prevent to creat gds bo as per-vm-bo. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Emily Deng authored
As now enabled per vm bo feature, the user mode driver won't supply the bo_list generally, for this case, the gdb_base, gds_size, gws_base, gws_size and oa_base, oa_size won't be set. v2: fix warning (Chunming) Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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- 29 May, 2018 18 commits
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Leo (Sunpeng) Li authored
For cases where the CRTC is inactive (DPMS off), where a modeset is not required, yet the CRTC is still in the atomic state, we should not attempt to update anything on it. Previously, we were relying on the modereset_required() helper to check the above condition. However, the function returns false immediately if a modeset is not required, ignoring the CRTC's enable/active state flags. The correct way to filter is by looking at these flags instead. Fixes: e277adc5 "drm/amd/display: Hookup color management functions" Bugzilla: https://bugs.freedesktop.org/106194Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Nikola Cornij authored
DP 1.4 compliance now requires that registers at DP_SINK_COUNT_ESI range (0x2002-0x2003, 0x200c-0x200f) are read instead of DP_SINK_COUNT range (0x200-0x2005. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nikola Cornij authored
DP 1.4 compliance requires 16 bytes to be read when reading link caps, i.e. it requires DP_ADAPTER_CAP to be included. Included it for all DP versions because reading more than required won't fail. Signed-off-by:
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Mikita Lipski authored
Prevent interrupt programming of a crtc on which the stream is disabled and it doesn't have an OTG to reference. Signed-off-by:
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Dmytro Laktyushkin authored
This change will fix wb and display scaling when ratios of 4 or more are involved Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
When a DRM mode reset is called on resume, the connector state's destructor is not called. This leaves a dangling reference on the CRTC commit object, which was obtained by the connector state during commit setup. Signed-off-by:
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Eric Bernstein authored
Add register programming to support TMZ and DCC on secondary surfaces. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Bernstein authored
Add register programming to support 16bpc component depth for DP. Signed-off-by:
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Roman Li authored
Fixing warning on dce10 with HDMI display. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Mikita Lipski authored
If connector doesn't have a sink, fake sink is created, but never released as it assumed that its destroyed with the stream it is used for. But now sink is released before the stream maintaing refcount consistency. This way we also avoid assigning anything to connector keeping all the operation local. Signed-off-by:
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Roman Li authored
FBC enabling and disabling path has msleep which leads to BUG hit when called in atomic context, hence this patch replaces msleeps with udelays appropriately. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Mikita Lipski authored
Delete if statement that would force any display's color depth higher than 8 bpc to 8 Signed-off-by:
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Leo Liu authored
It should be stateless, and no need for scheduler to take care specially. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Deepak Sharma authored
Move logic of getting supported domain to a helper function Signed-off-by:
Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-by:
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Deepak Sharma authored
When vram size <= THRESHOLD(256M) lets use GTT for dumb buffer allocation. As SG will be enabled with vram size <= 256M scan out will not be an issue. v2: Use amdgpu_display_supported_domains to get supported domain. Signed-off-by:
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Mikita Lipski authored
Add case options to retrieve either physical or display clocks with voltage from SMU controller that are needed by display driver. Signed-off-by:
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Harry Wentland authored
Also drop wrong 10kHz comment Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Signed-off-by:
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- 25 May, 2018 4 commits
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Nayan Deshmukh authored
When checking for a dependency fence for belonging to the same entity compare it with scheduled as well finished fence. Earlier we were only comparing it with the scheduled fence. Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
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kbuild test robot authored
Fixes: 9b4c412a654c ("drm/amdgpu: Add static CG control for VCN on RV") Signed-off-by:kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
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Harry Wentland authored
This is required so we use the correct minimum clocks for Vega. Without this pplib will never be able to enter the lowest clock states. Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Last feature request for 4.18. Mostly vega20 support. - Vega20 support - clock and powergating for VCN - misc bug fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180524152427.32713-1-alexander.deucher@amd.com
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- 24 May, 2018 8 commits
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David Francis authored
In fixed31_32.h, in dc_fixpt_shl,'/' was used for division of one long long int by another long long int. As there is no inbuilt long long int division function in c, gcc inserted its own. However, gcc does not link the library that contains this function. To avoid this, use bitwise operators instead of / Reviewed-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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Shaoyun Liu authored
Update to the latest version from the vbios team. Signed-off-by:
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Alex Deucher authored
is_dpm_running callback was assigned to the same value twice. Drop the duplicate. Reviewed-by:
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Emily Deng authored
To free the fence from the amdgpu_fence_slab, need twice call_rcu, to avoid the amdgpu_fence_slab_fini call kmem_cache_destroy(amdgpu_fence_slab) before kmem_cache_free(amdgpu_fence_slab, fence), add rcu_barrier after drm_sched_entity_fini. The kmem_cache_free(amdgpu_fence_slab, fence)'s call trace as below: 1.drm_sched_entity_fini -> drm_sched_entity_cleanup -> dma_fence_put(entity->last_scheduled) -> drm_sched_fence_release_finished -> drm_sched_fence_release_scheduled -> call_rcu(&fence->finished.rcu, drm_sched_fence_free) 2.drm_sched_fence_free -> dma_fence_put(fence->parent) -> amdgpu_fence_release -> call_rcu(&f->rcu, amdgpu_fence_free) -> kmem_cache_free(amdgpu_fence_slab, fence); v2:put the barrier before the kmem_cache_destroy v3:put the dma_fence_put(fence->parent) before call_rcu in drm_sched_fence_release_scheduled Signed-off-by:
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Christian König authored
Move all BOs belonging to a VM on the LRU with every submission. Signed-off-by:
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Christian König authored
Instead of sometimes checking if the vm_status is empty use the moved flag and also reset it when the BO leaves the state machine. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Christian König authored
In theory it is possible that PDs/PTs can move without eviction. Signed-off-by:
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Christian König authored
Splice the moved list to a local one to avoid taking the lock over and over again. Signed-off-by:
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