- 19 Feb, 2018 40 commits
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Mikita Lipski authored
Inside amdgpu_gtt_mgr_fini add a missing lock to maintain locking balance Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Start to use amdgpu_bo_create_reserved v2. v2: Fix missing pointer init to NULL. Remove extra new lines. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Christian König authored
We didn't synced the BO after validating it. Also sart to use amdgpu_bo_create_reserved to simplify things. Signed-off-by:
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Harry Wentland authored
Missed that with a previous change that removed unused files. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Christian König authored
The subsystem should check that, not the driver. Signed-off-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Christian König authored
The subsystem should check that, not the driver. Signed-off-by:
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Christian König authored
Stop calling the driver callback directly. Signed-off-by:
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Matthias Kaehlcke authored
calcs uses the compiler option -mpreferred-stack-boundary=4 to configure a stack alignment of 16 bytes. Clang uses the option -mstack-alignment instead, which expects as parameter the alignment in bytes, and not a power of two like -mpreferred-stack-boundary. Probe for both compiler options and use the correct one, similar to what is done in arch/x86/Makefile. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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Matthias Kaehlcke authored
DML uses the compiler option -mpreferred-stack-boundary=4 to configure a stack alignment of 16 bytes. Clang uses the option -mstack-alignment instead, which expects as parameter the alignment in bytes, and not a power of two like -mpreferred-stack-boundary. Probe for both compiler options and use the correct one, similar to what is done in arch/x86/Makefile. Reported-by:
Guenter Roeck <groeck@chromium.org> Signed-off-by:
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Matthias Kaehlcke authored
Use a variable for common CFLAGS instead of specifying the same flags for every source file. Signed-off-by:
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Matthias Kaehlcke authored
Use a variable for common CFLAGS instead of specifying the same flags for every source file. Signed-off-by:
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Shaoyun Liu authored
Add common smu_soc_asic_init function to emulate the sillicon post sequence Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
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Shaoyun Liu authored
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Shaoyun Liu authored
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Shaoyun Liu authored
On emulation mode , driver will be loaded with powerplay disabled Signed-off-by:
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Shaoyun Liu authored
Add amdgpu_emu_mode module parameter to control the emulation mode Avoid vbios operation on emulation since there is no vbios post duirng emulation, use the common hw_init to simulate the post Signed-off-by:
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Kai-Heng Feng authored
The affected system (0x0813) is pretty similar to another one (0x0812), it also needs to use ATPX power control. Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Rex Zhu authored
As auto power profile mode still not support on vega10, so just restore default profile mode in auto dpm level. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
v2: change power unit to microWatt Adust power limit through power1_cap Get min/max power limit through power1_cap_min/power1_cap_max Reviewed-by:
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Rex Zhu authored
User can change power limit between [0, 1] * max power limit. Set power limit to 0, restore to max power limit. Reviewed-by:
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Matthias Kaehlcke authored
The driver passes GRAPHICS_CSC_ADJUST_TYPE_SW of type enum graphics_csc_adjust_type to program_color_matrix(), however the function expects a parameter of type enum grph_color_adjust_option. Supposedly the intention was to pass GRPH_COLOR_MATRIX_SW, which has the same value as GRAPHICS_CSC_ADJUST_TYPE_SW, so the mismatch didn't cause any trouble. Pass GRPH_COLOR_MATRIX_SW to program_color_matrix() instead of GRAPHICS_CSC_ADJUST_TYPE_SW, this also fixes the following warning when building the kernel with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1129:24: error: implicit conversion from enumeration type 'enum graphics_csc_adjust_type' to different enumeration type 'enum grph_color_adjust_option' [-Werror,-Wenum-conversion] xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); Signed-off-by: -
Matthias Kaehlcke authored
The double parentheses are not needed. Removing them fixes multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:617:42: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if ((data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling)) { Signed-off-by: -
Shaoyun Liu authored
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Matthias Kaehlcke authored
The double parentheses are not needed. Removing them fixes the following warning when building with clang: drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c:419:29: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) { Reviewed-by: -
Matthias Kaehlcke authored
In several locations the driver uses AMD_CG_STATE_UNGATE (type enum amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum amd_powergating_stat) and vice versa. Both constants have the same value, so this doesn't cause any problems, but we still want to pass the correct type. Fixing the mismatch resolves multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7: error: implicit conversion from enumeration type 'enum amd_powergating_state' to different enumeration type 'enum amd_clockgating_state' [-Werror,-Wenum-conversion] AMD_PG_STATE_UNGATE); Reviewed-by: -
Eric Huang authored
PSP will disable legacy mmhub PG setting that is programming registers, and drive will use SMC message to set it up. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
new generic interface is added in powerplay. Signed-off-by:
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Eric Huang authored
mmhub PG is enabled by SMU FW only for Raven. Signed-off-by:
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Eric Huang authored
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Dan Carpenter authored
We deleted some code in e154162e ("drm/amd/powerplay: refine pp code for raven") but there were a few related bits that were missed. Let's delete them as well. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Tom St Denis authored
Since 12 of the 16 bytes are not initialized with anything let's ensure they're sensibly zeroed out otherwise debugfs callers will read back garbage (because they assume debugfs wrote sensible data back...) Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Tony Cheng authored
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Krunoslav Kovac authored
There are several optimizations: 1) Use predefined SRGB, don't calculate. This is the most common case. 2) Precompute HW X points at boot since they're fixed in ColModule 3) Precompute PQ - it never changes and is very CPU intensive in fixed pt. 4) Reduce number of points in ColModule to 512 (32x16) from 1024. This also requires reducing some regions for legacy DCEs to 16 pts at most. Performance 1) is super-fast, build_output_tf is 1-2us, down from 25000-30000. Programming also fast since only one reg write. 2)+3) gives build_output_tf for PQ in ~100us range, down from ~80000-110000 2) + 4) results in slightly over 50% improvement. It gives an idea of the savings when we can't use SRGB or PQ table (e.g. sdr white level > 80). There's also a bit of refactoring: renaming some stuff that was misleading and removing a lot of magic numbers that novices might not be able to understand where they come from and what they mean. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Charlene Liu authored
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Charlene Liu authored
Signed-off-by:
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Tony Cheng authored
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John Barberiz authored
Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
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Yongqiang Sun authored
System soft hang when hotplug specific 4K DP panel due to link caps read error and incorrect link setting parmas to enable dp. Add status check for DPCD read and add return value for detect dp, in case of false, return from caller, avoid further false operation. Signed-off-by:
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