1. 15 Aug, 2016 24 commits
  2. 13 Aug, 2016 11 commits
  3. 12 Aug, 2016 4 commits
    • Fabio Estevam's avatar
      clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRC · 1fd92dba
      Fabio Estevam authored
      Booting the kernel on a imx7s-warp leads to several warnings like these:
      
      [    0.000000] ------------[ cut here ]------------
      [    0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330
      [    0.000000] releasing a pinned lock
      
      [    0.000000] ------------[ cut here ]------------
      [    0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4
      [    0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled))
      
      [    0.000000] ---[ end trace cb88537fdc8fa201 ]---
      [    0.000000] bad: scheduling from the idle thread!
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W       4.7.0-rc7-next-20160715 #404
      
      [    0.000000] ------------[ cut here ]------------
      [    0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8
      [    0.000000] Modules linked in:
      
      [    0.000591] ------------[ cut here ]------------
      [    0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8
      
      [    0.002084] ------------[ cut here ]------------
      [    0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0
      [    0.002114] Interrupts were enabled early
      
      This fix is along the same lines as 5e33ebff ("clk: imx7d: do not
      set parent of ethernet time/ref clocks") and the explanation from that
      commit is:
      
      "The reason for the warning is that setting the parent enables the ENET
       PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
       cause clk_pllv3_wait_lock to sleep. See also:
       commit fc8726a2 ("clk: core: support clocks which requires parents
       enable (part 2)")."
      
      imx7s-warp does not even use the FEC interface, so we should not really
      configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock
      driver code.
      
      The dts file should use the assigned-clocks/assigned-clock-parents method,
      so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      1fd92dba
    • Stephen Boyd's avatar
      MAINTAINERS: Add linux-clk patchwork URL · 22d61acf
      Stephen Boyd authored
      The common clk framework has a patchwork associated with it.
      Update the maintainers file to reflect this.
      
      Cc: Michael Turquette <mturquette@baylibre.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      22d61acf
    • Michael Turquette's avatar
      clk: migrate ref counts when orphans are reunited · 904e6ead
      Michael Turquette authored
      It's always nice to see families reunited, and this is equally true when
      talking about parent clocks and their children. However, if the orphan
      clk had a positive prepare_count or enable_count, then we would not
      migrate those counts up the parent chain correctly.
      
      This has manifested with the recent critical clocks feature, which often
      enables clocks very early, before their parents have been registered.
      
      Fixed by replacing the call to clk_core_reparent with calls to
      __clk_set_parent_{before,after}.
      
      Cc: James Liao <jamesjj.liao@mediatek.com>
      Cc: Erin Lo <erin.lo@mediatek.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      [sboyd@codeaurora.org: Recalc accuracies and rates too]
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      904e6ead
    • Yoshihiro Shimoda's avatar
      clk: renesas: r8a7795: Fix SD clocks · e0cb1b84
      Yoshihiro Shimoda authored
      According to the datasheet, SDn clocks are from the SDSRC clock. And
      the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal
      core clock. Otherwise, since the sdhi driver will calculate clock for
      a sd card using the wrong parent clock rate, and then performance will
      be not good.
      
      Fixes: 90c073e5 ("clk: shmobile: r8a7795: Add SD divider support")
      Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
      Acked-by: default avatarDirk Behme <dirk.behme@de.bosch.com>
      Tested-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      e0cb1b84
  4. 10 Aug, 2016 1 commit