From Jason Cooper:
mvebu dt for v3.10 round 3

 - mvebu PCIe DT support

from round 2 (no pr was sent):
 - 64bit dts skeleton
 - mvebu devicebus additions
 - mvebu thermal nodes
 - mirabox gpio leds
 - orion5x xor and ehci
 - use mvsdio on guruplug dt

* tag 'dt-3.10-3' of git://git.infradead.org/users/jcooper/linux:
  arm: mvebu: PCIe Device Tree informations for Armada XP GP
  arm: mvebu: PCIe Device Tree informations for Armada 370 DB
  arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
  arm: mvebu: PCIe Device Tree informations for Armada XP DB
  arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
  arm: mvebu: add PCIe Device Tree informations for Armada XP
  arm: mvebu: add PCIe Device Tree informations for Armada 370
  ARM: dts: Add a 64 bits version of the skeleton device tree
  ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
  ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
  ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
  ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
  ARM: configs: Update mvebu defconfig for thermal
  ARM: mvebu: Add thermal support to Armada 370 device tree
  ARM: mvebu: Add thermal support to Armada XP device tree
  arm: mvebu: Add GPIO LEDs to Mirabox board
  arm: orion5x: enable xor for orion5x platform
  arm: orion5x: add ehci bindings to dtsi
  ARM: kirkwood: make use of DT mvsdio on guruplug board
  ARM: mvebu: Add button on Armada 370 Reference Design board

The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

This patch adds the required node for the SDHC controller on WM8505 SoCs.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Olof Johansson <olof@lixom.net>

In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

This patch selects the devbus driver as part of the mvebu default
config, along with the required options to detect and support
CFI flash memories.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Plat'home Openblocks AX3 has a 128 MiB NOR flash device connected
to the Device Bus. This commit adds the device tree node to support this device.

The SoC supports a flexible and dynamic decoding window allocation scheme;
but since this feature is still not implemented we need to specify the window
base address in the device tree node itself.
This base address has been selected in a completely arbitrary fashion.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The Armada XP Development Board DB-MV784MP-GP has a NOR flash device
connected to the Device Bus. This commit adds the device tree node
to support this device.

This SoC supports a flexible and dynamic decoding window allocation
scheme; but since this feature is still not implemented we need
to specify the window base address in the device tree node itself.

This base address has been selected in a completely arbitrary fashion.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Armada 370 and Armada XP SoC have a Device Bus controller to
handle NOR, NAND, SRAM and FPGA devices.
This patch adds the device tree node to enable the controller.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

From Maxime Ripard:
SunXi dt additions for 3.10, take 3
  - Remove sunxi.dtsi and only use one dtsi for each SoC
  - Various compatible renamings to be consistent with the other platforms

* tag 'sunxi-dt-for-3.10-3' of git://github.com/mripard/linux:
  ARM: sunxi: dt: Update watchdog compatible string
  ARM: sunxi: dt: Update interrupt controller compatible string
  ARM: sunxi: dt: Update timer compatible string
  ARM: sunxi: dt: Reorganize the dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'tegra-for-3.10-fixes-for-mmc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt

From Stephen Warren <swarren@wwwdotorg.org>:

ARM: tegra: DT-related fixes needed by the MMC tree

In order to convert the Tegra MMC driver to using mmc_of_parse(), some
bugs in the Tegra device-tree content need to be fixed first; it's
currently wrong but unused, and mmc_of_parse() causes that data to be
used for the first time.

* tag 'tegra-for-3.10-fixes-for-mmc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

From Nicolas Ferre <nicolas.ferre@atmel.com>:

One macb DT node move for 9x5 family: 9g15 doesn't
have an Ethernet interface.
Little fixes mainly related to at91sam9x5 DT, IIO ADC bindings,
pinctrl for at91sam9260/g20 DT and the RTC addition.
Addition of the Acme Systems Aria G25 board.

* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
  ARM: at91/at91sam9260.dtsi: fix u(s)art pinctrl encoding
  ARM: at91: dts: add adc resolution stuff
  ARM: at91: add Acme Systems Aria G25 board
  ARM: at91/dt: fix macb node declaration
  ARM: at91: remove partial parameter in bootargs for at91sam9x5ek.dtsi
  ARM: at91/trivial: fix model name for SAM9G15-EK
  ARM: at91/trivial: typos in compatible property
  ARM: at91/at91sam9x5: add RTC node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

In the early days, the A10 and A13 shared quite some code. Nowadays it
shares less and less code, the A31 diverging even more, so it doesn't
make much sense to continue to maintain this structure, just use one
DTSI for every SoC, and that's it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

From Maxime Ripard <maxime.ripard@free-electrons.com>:

ARM: sunxi: dt additions for 3.10, take 2

  - Rename the clock compatible introduced in the first pull request for 3.10
  - Complete the UART support for A13 and A10
  - Adds clock gates support

* tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux:
  arm: sunxi: Add clock to pinctrl node
  arm: sunxi: use the right clock phandles for UARTs
  arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
  ARM: sunxi: cubieboard: Add UART muxing
  ARM: sunxi: hackberry: Add UART muxing
  ARM: sunxi: dt: Add A10 UARTs to the dtsi.
  ARM: sunxi: dt: Add uart3 dt node
  ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
  ARM: sunxi: Rename uart nodes to serial
  ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
  arm: sunxi: rename clock compatible strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/dt

From Stephen Warren <swarren@wwwdotorg.org>:

ARM: bcm2835: device tree updates

This branch adds two devices to the BCM2835 SoC device tree: the SPI
controller and the HW random number generator.

The SPI controller isn't actually instantiated in the Raspberry Pi
device tree, since there are no on-board SPI devices; it's up to the
end-user to modify their own device-tree to describe whatever they
have attached.

* tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
  ARM: bcm2835: add Broadcom BCM2835 RNG to the device tree
  ARM: bcm2835: add SPI device to DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

From Michal Simek <michal.simek@xilinx.com>:

It enables pmu support for zynq.
* 'zynq/core' of git://git.xilinx.com/linux-xlnx:
  arm: zynq: Add support for pmu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The port controller needs the apb0_pio clock enabled to be able to
work. This commit declares that on the device tree.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

All the UARTs are connected to clock gates; now that our clock driver
is able to handle them, make the switch.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This commit adds the corresponding DT bindings for all the AXI,
AHB, APB0 and APB1 gates.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: Douglas Gilbert <dgilbert@interlog.com>
[nicolas.ferre@atmel.com: fix rts/cts for usart3]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> [3.8+]

Add the ADC low and high resolution configuration and which one to use.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: Douglas Gilbert <dgilbert@interlog.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Macb0 node cannot be activated in generic sam9x5ek.dtsi file
as the sam9g15 does not have one.
Move the macb0 & macb1 activation in board .dts file that
support them.
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Zynq is standard PMU with 2 interrupt per core.
There is also access via register which is not used right now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

This adds a device tree binding for random number generator present on
Broadcom BCM2835 SoC, used in Raspberry Pi and Roku 2 devices.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

The thermal management driver for Armada XP/370 has been added
so we update the defconfig to reflect this.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

This patch adds support for the thermal controller available in
all Armada 370 boards. This controller has two 4-byte registers:
one to read the thermal sensor, the other for sensor initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

This patch adds support for the thermal controller available in
all Armada XP boards. This controller has two 4-byte registers:
one to read the thermal sensor, the other for sensor initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Add the three external LED definitions to the device tree file on
the Mirabox.

The Mirabox user guide calls out one as a power LED, and the other
two are defined for WiFi, but as the current mwifiex drivers don't
have LED support, we make them status LEDs.

These have been tested working by writing to the appropriate
/sys/class/leds trigger.
Signed-off-by: Ryan Press <ryan@presslab.us>
Tested-by: Neil Greatorex <neil@fatboyfat.co.uk>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The orion5x SoC includes DMA functionality, so lets enable that
and turn it on by default.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

The orion5x SoC also includes a USB EHCI componment so lets add that
to the dtsi (disable by default incase the pins are not broken out).
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Device tree based guruplug boards still use mvsdio platform_data and
kirkwood_sdio_init to enable sdio. DT support for sdio is already there,
so make use of it.

This also fixes mvsdio accidentially breaking nand by configuring mpp0
to gpio, while used also by nand (nand_io2 on mpp0).
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Soeren Moch <smoch@web.de>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>