- 22 Jun, 2019 40 commits
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Eryk Brol authored
[Why] In order to ensure that incoming flips are latched and complete immediately, we need to program the vupdate interrupt to come during the back porch of each frame. [How] Program the vupdate start_line to be in the back porch like it's done for DCN1. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yongqiang Sun authored
Refactor programming watermark function: Divided into urgent watermark, stutter watermark and pstate watermark. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dmytro Laktyushkin authored
The split condition is broken and will always activate at the moment. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Charlene Liu authored
Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1 and DCN2. In addition, future HW will need to access the HUBPREQ_DEBUG and CUR_TTU_CNTL0 register for hubp_init. Add that here. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Ilya Bakoulin authored
[Why] OPTC data format was left at its default value (444) when enabling ODM combine. This caused issues with FPGA capture. [How] Write the OPTC_DATA_FORMAT field when enabling ODM combine. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Yongqiang Sun authored
Signed-off-by:
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Thomas Lim authored
[Why] Due to the generic introduction of seamless boot, the display is no longer blanked upon boot. However, this causes corruption on some systems that does not lock the memory in the non-secure boot case, resulting in brief corruption on boot due to garbage being written into the frame buffer. [How] Add a flag, read during DC init, to determine whether display should be blanked on boot. Default to true. Signed-off-by:
Thomas Lim <Thomas.Lim@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Nikola Cornij authored
[why] DSC target bpp precision is a decoder DPCD and an AMD encoder capability. It must be taken into account when calculating target bitrate. [how] Add a DC DSC function that does this calculation. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Josip Pavic authored
[Why] ABM is currently not enabled on DCN2. [How] Update the register name list for DCN2 and un-comment the code that creates the abm object. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] The current policy will always enable DSC to 12 bpp regardless of if the current bandwidth is enough for MST displays. This logic is not optimal because user will get lower quality output if DSC compression is enabled. This change to is to implement a DSC MST bandwidth fair share algorithm so we will dynamically decide if DSC is needed and what quality (target bpp) is needed to fairly destribute the MST bandwidth in one MST topology. This will allow user to see the most optimal image quality with the given bandwidth. [how] We will start with lowest bandwidth possible and run a Max-Min fairness algorithm to fairly distribute the available bandwidth. If there is still remaining bandwidth, we will try to fit the timing without DSC compression. Signed-off-by:
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Nikola Cornij authored
[why] There are ASICs that have fewer DSC engines than pipes, which makes DSC a resource that should be used only if required. [how] Acquire DSC HW resource if required by stream and release when not required anymore. Signed-off-by:
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hersen wu authored
[WHY] system crash when initialize dwb current linux driver does not support dwb. disable this feature for now. [HOW] set num_dwb = 0 to disable dwb for now Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
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hersen wu authored
[WHY] linux upstream already has interrupt vupdate for freesync in dcn10. dcn20 interrupt shares the same source code as dcn10. but dcn20 interrupt translator does not add vupdate interrupt. this cause index of vupdate aarray be negative which causes crash. [HOW] add vupdate into dc interrupt transltor Signed-off-by:
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Nikola Cornij authored
[why] DSC resource has to be acquired before it can be used and simply copying a reference to it is very likely to cause problems when accessing DSC. [how] Set DSC resource pointer to NULL to mark it as unused after primary pipe resources were copied to the secondary ODM pipe. Signed-off-by:
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Tyler DiBattista authored
[Why] Some nightly tests are failing since the new value for fclk is a bit too low. Also, a new test for the maximum downscale case was needed. [How] Updated the default value for fclk to be 1.2GHz. Signed-off-by:
Tyler DiBattista <tyler.dibattista@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] when an update programming sequence requires both front end and back end pipe to be updated synchronously, a global update lock needs to be set to ensure that we don't get a frame with only front end update but not the back end update. [how] setup global lock parameters on enable_stream_timing. enable global lock when pipe_control_lock_global is called. disable global lock when pipe_control_lock is called. Signed-off-by:
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Yongqiang Sun authored
[Why] Some register fields are not needed. [How] remove them Signed-off-by:
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Joshua Aberback authored
[Why] We used this change to investigate the performance of bandwidth validation, it will be useful to have if we need to investigate further. [How] We use performance counter tick numbers to profile performance, they live at dc->debug.bw_val_profile (set .enable in debugger to turn on measuring). Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
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Joshua Aberback authored
We can split validation into three parts: getting voltage level, getting watermarks, and rq/dlg calculations. The voltage level is enough to answer the question "do we support this state", and the rest of it is to determine what hardware programming is needed to support the state. Most of the calls to validate_bandwidth only care about the first part, so we added an early return in that case Signed-off-by:
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Leo Li authored
[Why] display_mode_vba is for DCN2 and up. When building for upstream (DCN1 enabled only), there will be a build error, since display_mode_vba.c/h is stripped out. Note that building DCN1 only with internal dal-dev is still fine, since display_mode_vba.h is not stripped out internally - only in upstream. The make directives therefore stll work, and so will any #include's. [How] Since subsequent generations require DCN2 enabled anyways, guard the makefile directive for display_mode_vba.o with DCN2. Guard any includes with DCN2. In addition, guard the entire contents of display_mode_vba.h with DCN2, to simulate the file being stripped out in upstream. A forward declaration for 'struct display_mode_lib' also needs to be added in display_mode_lib.h. Previously, display_mode_vba.h contained the forward declaration, and display_mode_lib.h in turn included it. This won't work if mode_vba.h is stripped out, requring mode_lib.h to do so itself. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Leo Li authored
[Why] Usage of this enum is DSC-only. [How] Guard it with CONFIG_DRM_AMD_DC_DSC_SUPPORT. Signed-off-by:
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Vitaly Prosyak authored
[Why & How] The follow up change Improve some naming for fields and structs Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Charlene Liu authored
[Why] Can not turn on two displays at the same time with the asic having only one DSC. DC_DSC_RESOURCE allocation failed. [Solution] Only add_dsc if the timing is dsc capable based on diag_dc and num_dsc Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Ilya Bakoulin authored
[Why] If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML calculations, which ended up causing an assert. [How] Initialize dcfclk_mhz and socclk_mhz values according to the voltage level. Signed-off-by:
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Yongqiang Sun authored
Added some regs and exposed some functions for future use Signed-off-by:
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Vitaly Prosyak authored
Move flags from color_gamma.h to mod_shared.h and add more options and setting structures Signed-off-by:
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Nikola Cornij authored
[why] DSC spec requires this Signed-off-by:
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Nikola Cornij authored
[why] On at least some of the devices (e.g. Realtek scaler) we get a black screen if 1/16th precision is used. [how] Work around it by reducing precision to 1/8th for N4:2:2 and 4:2:0 color formats. This is a safe workaround and would have a very mild impact on the quality. The issue is still to be root-caused and fixed correctly. Signed-off-by:
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Wenjing Liu authored
[why] Global optic double buffer lock is currently disabled due to incorrect programming sequence that affects non global lock. [how] Isolate global lock programming sequence out of non global lock programming sequence, so it can be enabled without affecting non global lock. Signed-off-by:
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Nikola Cornij authored
[why] This is now done in the original link bandwidth calculation and DSC must not do this anymore. [how] Remove the line of code that should have been removed when transition to correctly applying FEC overhead was made. Signed-off-by:
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Tony Cheng authored
code restructure. Signed-off-by:
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Dmytro Laktyushkin authored
We shouldnt need overhead on top of dppclk when setting fclk. Signed-off-by:
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Wenjing Liu authored
Remove dc_dsc hack for MST policy Signed-off-by:
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Wenjing Liu authored
[why] Clean up some dsc legacy functions that are no longer needed. [how] remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing instead of calc_required_bandwidth_for_timing. Signed-off-by:
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Joshua Aberback authored
[Why] dcn20_apply_ctx_for_surface can be called with 0 planes, which means we should blank the display. In this case when we get down to dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't check for it. However, this function is only called by dcn20_pipe_control_lock, and in that function we alraedy have a local for the immediate flip status, which is what we care about in the plane state. [How] - pass in immediate flip status as parameter Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Currently dsc is validated not taking the image width limitation into mind. This change addresses that, but due to previous design being limited to non odm dsc validation additional sequence changes are made. Signed-off-by:
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Aidan Wood authored
[Why] u clk set request was being sent in units of mts, when it needed to be in units of Mhz [How] add a division by 16 to convert from mts to Mhz Signed-off-by:
Aidan Wood <Aidan.Wood@amd.com> Reviewed-by:
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Aidan Wood authored
[Why] If num_states == 0 we did update_bound_box which doesn't updated any max clocks if num_states == 0, therefore we need to do cap_soc_clocks instead, also SMU cannot set DCF clock to a higher than or equal to freq than SOC clock [How] Add a num_states != 0 check for update_bounding_box to be run, and after we run get_maximum_sustainable_clocks we now check if the reported max value of DCF is higher than SOC and if necessary set it to 1000 (becomes 1 after division by 1000) lower than SOC Signed-off-by:
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Nikola Cornij authored
[why] Currently link bandwidth is calculated in various places using the same multi-step formula. Doing this in one common place makes sure the same formula will indeed be applied to all link bandwidth calculations. It also makes it possible to apply link-setting-specific adjustments that affect effective link bandwidth. [how] Replace all implementations of link bandwidth calculation with a call to a function. Signed-off-by:
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Vitaly Prosyak authored
[Why & How] When TM is enabled with 3dlut, we apply conversion to dcip3 in gamut remap matrix, if source area less than dcip3. If it is bigger, we remap to bt2020. The added flags will be used to facilitate this logic. Signed-off-by:
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