This patch allows to build the Kernel for Vybrid (VF6xx) SoC
when ARMv7-M CPU is selected. The resulting image runs on the
secondary Cortex-M4 core. This core has equally access to all
peripherals as the main Cortex-A5 core. However, there is no
resource control mechanism, hence when both cores are used
simultaneously, orthogonal device tree's are required.

The boot CPU is dependent on the SoC variant. The available
boards use mostly variants where the Cortex-A5 is the primary
and hence the boot CPU. Booting the secondary Cortex-M4 CPU
needs SoC specific registers written. There is no in kernel
support for this right now, a external userspace utility
called "m4boot" can be used to boot the kernel:

m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This introduces a new top level config symbol ARM_SINGLE_ARMV7M
for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M
platforms in one kernel image since the cores share the same
basic memory layout and interrupt controller. However, this works
only if the combined platforms also have a similar (main) memory
layout.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Remove the needless differences between MMU/!MMU addruart calls.
This allows to use the same addruart macro on SoC level. Useful
for SoC consisting of multiple CPUs with and without MMU such as
Freescale Vybrid.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* 'irq/for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: vf610-mscm: Support NVIC parent chip
  irqchip: nvic: Support hierarchy irq domain
  genirq: generic chip: Support hierarchy domain
  genirq: Add irq_chip_(enable/disable)_parent
  irqdomain: Add non-hierarchy helper irq_domain_set_info

This pull request for the MAINTAINERS file contains the following changes:

- Brian adds a general "brcmstb" regexp to catch Broadcom Set Top Box related
  changes throughout the Linux tree

* tag 'arm-soc/for-4.2/maintainers' of http://github.com/broadcom/stblinux:
  MAINTAINERS: add brcmstb regex

Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek:

- Change SoC reset path
- Fix SLCR unlock scheme

* tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart
  ARM: zynq: Use restart_handler mechanism for slcr reset

This makes uniphier behave like all the other platforms that
support TWD, and only select this driver when SMP is enabled.
Without this, we get a compile error on UP builds:

arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register':
arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Using a dedicated symbol for low-level debugging instead of the
arch symbol will make this platform play nice when enabled on a
kernel that supports multiple platforms.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add a MAINTAINER entry covering all NXP LPC18xx/43xx
machine and drivers files.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Support the NVIC interrupt controller as node parent of the MSCM
interrupt router. On the dual-core variants of Vybird (VF6xx), the
NVIC interrupt controller is used by the Cortex-M4. To support
running Linux on this core too, MSCM needs NVIC parent support too.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-6-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Add support for hierarchy irq domains. This is required to stack
the MSCM interrupt router and the NVIC controller found in Vybrid
SoC.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-5-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Use the new helper function irq_domain_set_info to make sure the
function irq_domain_set_hwirq_and_chip is being called, which is
crucial to save irqdomain specific data to irq_data.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-4-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Add helper irq_chip_enable_parent and irq_chip_disable_parent. The
helper implement the default behavior in case irq_enable or irq_disable
is not implemented for the parent interrupt chip, which is calling the
irq_mask or irq_unmask respectively.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-3-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

This adds the helper irq_domain_set_info() in a non-domain hierarchy
variant. This allows to use the helper for generic chip since not
all chips using generic chip support domain hierarchy.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Cc: marc.zyngier@arm.com
Cc: linux@arm.linux.org.uk
Cc: u.kleine-koenig@pengutronix.de
Cc: olof@lixom.net
Cc: arnd@arndb.de
Cc: daniel.lezcano@linaro.org
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: ijc+devicetree@hellion.org.uk
Cc: galak@codeaurora.org
Cc: mcoquelin.stm32@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1431769465-26867-2-git-send-email-stefan@agner.chSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
and not ever re-locked. As such, it is not necessary to explicitly unlock in
the restart codepath.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.

Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add a MAINTAINER entry covering all STM32 machine and drivers files.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add entry for ZTE ARM architecture
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Bring up the secondary core. Enable hotplug with supporting
powering off secondary core.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Use the UART0 peripheral for low level debug. Only the UART port 0 is
currently supported.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add basic code for ZTE ZX296702 platform.

[arnd: removed unused zx296702_init_machine function, and changed
       l2c aux val to default]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4)
SoCs. These SoCs are NXP's high preformance MCU line and can run at
clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx.

LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few
extra peripherals. The LPC43xx series also features one or two
Cortex-M0 cores that can be used to offload the main M4 core.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge "pxa changes for v4.2 cycle" from Robert Jarzmik:

The main and only feature is the conversion of all pxa variants to clock
framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.

This should be a disruptive cycle in the normally quiet pxa history, as
the change can break any platform, and the test were performed on only 4
boards (lubbock, zylonite, mioa701, cm-x300).

* tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux:
  ARM: pxa: Constify irq_domain_ops
  ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
  ARM: pxa: convert eseries to clock framework
  ARM: pxa: Transition pxa25x and pxa27x to clk framework
  ARM: pxa: pxa27x skip default device initialization with DT
  clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc
  ARM: pxa: move gpio11 clock to board files
  ARM: pxa: change clocks init sequence

Merge tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/soc

Merge "RaspberryPi SoC (mach) changes due for v4.2" from Lee Jones:

* tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi:
  ARM: bcm2835: Move the restart/power_off handling to the WDT driver
  ARM: bcm2835: Drop the init_irq() hook
  ARM: bcm2835: Skip doing our own iotable_init() initialization

Since the WDT is what's used to drive restart and power off, it makes
more sense to keep it there, where the regs are already mapped and
definitions for them provided.  Note that this means you may need to
add CONFIG_BCM2835_WDT to retain functionality of your kernel.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

This is the default function that gets called if the hook is NULL.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

The only thing we were using this 16MB mapping of IO peripherals for
was the uart's early debug mapping.  If we just drop the map_io hook,
the kernel will call debug_ll_io_init() for us, which maps the single
page needed for the device.
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

This could probably consolidate a few file listings. And it satisfies
the spirit of the highly annoying [1] checkpatch warning for every new
file, though it sadly won't quash it.

[1] https://lkml.org/lkml/2014/12/17/24Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

Merge tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc

Merge "ARM: tegra: Core SoC changes for v4.2-rc1" from Thierry Reding:

A couple of changes to the core SoC support code. Perhaps the most
important part is a fix for a regression in LP1 suspend/resume code that
was introduced a while back.

* tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: move to using a restart handler
  ARM: tegra20: Store CPU "resettable" status in IRAM
  soc/tegra: Watch wait_for_completion_timeout() return type

Merge tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc

Merge "SoCFPGA updates for v4.2" from Dinh Nguyen:

- Add big endian support
- Add earlyprintk support on UART1 that is used on Arria10
- Remove the need to map uart_io_desc
- Use of_iomap to map the SCU
- Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
  the CPU mapping.

* tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: use of_iomap to map the SCU
  ARM: socfpga: remove the need to map uart_io_desc
  ARM: socfpga: Add support for UART1 debug uart for earlyprintk
  ARM: socfpga: support big endian for socfpga
  ARM: socfpga: enable big endian for secondary core(s)
  ARM: debug: fix big endian operation for 8250 word mode

Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove
map_io in socfpga.c.

Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is
already doing the CPU mapping.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.

This is the last step of clock framework transition for pxa
platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and
zylonite (pxa3xx).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

As pxa architecture transitions to clock framework, the previously
available INIT_CLKREG is no more. Use the fixed clock rate initializer
to declare the "fake" CLK_CK32K in eseries.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

Transition the PXA25x and PXA27x CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.

The transition breaks the previous clocks activation of pin
control (gpio11 and gpio12). Machine files should be amended to take
that into account.

This is the last step of clock framework transition for pxa25x and
pxa27x, leaving only pxa3xx for further work.
Reviewed-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

When booting via DT, the default PXA devices must not have been probed
before, otherwise the augmented information from the device tree is
ignored.

This is the twin commit of commit 82ce44d1 ("ARM: pxa3xx: skip
default device initialization when booting via DT").
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Daniel Mack <daniel@zonque.org>

Add 2 clocks which were erronously forgotten by the clock framework
port, namely :
 - sa1100-rtc
 - irda for pxa2xx-ir:UARTCLK
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Michael Turquette <mturquette@linaro.org>

The pxa25x gpio11 clock output was previously selected on its pin by the
clock enabling, toggling the pin function.

As we transition to common clock framework, the pin function is moved to
board file for the 2 users, ie. lubbock and eseries.
Reviewed-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

Since pxa clocks were ported to the clock framework, an ordering issue
appears between clocks and clocksource initialization. As a consequence,
the pxa timer clock cannot be acquired in pxa_timer, and is disabled by
clock framework because it is "unused".

The ordering issue is that in the kernel boot sequence :
  start_kernel()
    ...
    time_init()
      -> pxa_timer()
        -> here the clocksource is initialized
    ...
    rest_init()
      kernel_init()
	initcalls
	  -> here the clocks are initialized

In the current sequence, the clocks are initialized way after pxa_timer,
which cannot acquire the OSTIMER0 clock.

To solve this issue, the clocks initialization is moved to pxa_timer(),
so that clocks are initialized before clocksource for non device-tree.
For device-tree, the standard arm time_init() will take care of the
ordering.
Reviewed-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>