- 15 May, 2020 2 commits
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Ivan Khoronzhuk authored
AM65 CPSW h/w supports Enhanced Scheduled Traffic (EST – defined in P802.1Qbv/D2.2 that later got included in IEEE 802.1Q-2018) configuration. EST allows express queue traffic to be scheduled (placed) on the wire at specific repeatable time intervals. In Linux kernel, EST configuration is done through tc command and the taprio scheduler in the net core implements a software only scheduler (SCH_TAPRIO). If the NIC is capable of EST configuration, user indicate "flag 2" in the command which is then parsed by taprio scheduler in net core and indicate that the command is to be offloaded to h/w. taprio then offloads the command to the driver by calling ndo_setup_tc() ndo ops. This patch implements ndo_setup_tc() to offload EST configuration to CPSW h/w. Currently driver supports only SetGateStates operation. EST operates on a repeating time interval generated by the CPTS EST function generator. Each Ethernet port has a global EST fetch RAM that can be configured as 2 buffers, each of 64 locations or one large buffer of 128 locations. In 2 buffer configuration, a ping pong mechanism is used to hold the active schedule (oper) in one buffer and new (admin) command in the other. Each 22-bit fetch command consists of a 14-bit fetch count (14 MSB’s) and an 8-bit priority fetch allow (8 LSB’s) that will be applied for the fetch count time in wireside clocks. Driver process each of the sched-entry in the offload command and update the fetch RAM. Driver configures duration in sched-entry into the fetch count and Gate mask into the priority fetch bits of the RAM. Then configures the CPTS EST function generator to activate the schedule. Currently driver supports only 2 buffer configuration which means driver supports a max cycle time of ~8 msec. CPSW supports a configurable number of priority queues (up to 8) and needs to be switched to this mode from the default round robin mode before EST can be offloaded. User configures these through ethtool commands (-L for changing number of queues and --set-priv-flags to disable round robin mode). Driver doesn't enable EST if pf_p0_rx_ptype_rrobin privat flag is set. The flag is common for all ports, and so can't be just overridden by taprio configuration w/o user involvement. Command fails if pf_p0_rx_ptype_rrobin is already set in the driver. Scheds (commands) configuration depends on interface speed so driver translates the duration to the fetch count based on link speed. Each schedule can be constructed with several command entries in fetch RAM depending on interval. For example if each sched has timer interval < ~130us on 1000 Mb link then each sched consumes one command and have 1:1 mapping. When Ethernet link goes down, driver purge the configuration if link is down for more than 1 second. The patch allows to update the timer and scheds memory only if it's really needed, and skip cases required the user to stop timer by configuring only shceds memory. Signed-off-by:
Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Ivan Khoronzhuk authored
TAPRIO/EST offload support in CPSW2G requires EST scheduler function enabled in CPTS. So this patch add a function to set cycle time for EST scheduler. It also add a function for getting time in ns of PHC clock for taprio qdisc configuration. Mostly to verify if timer update is needed or to get actual state of oper/admin schedule. Signed-off-by:
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- 14 May, 2020 20 commits
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David S. Miller authored
Igor Russkikh says: ==================== net: qed/qede: critical hw error handling FastLinQ devices as a complex systems may observe various hardware level error conditions, both severe and recoverable. Driver is able to detect and report this, but so far it only did trace/dmesg based reporting. Here we implement an extended hw error detection, service task handler captures a dump for the later analysis. I also resubmit a patch from Denis Bolotin on tx timeout handler, addressing David's comment regarding recovery procedure as an extra reaction on this event. v2: Removing the patch with ethtool dump and udev magic. Its quite isolated, I'm working on devlink based logic for this separately. v1: https://patchwork.ozlabs.org/project/netdev/cover/cover.1588758463.git.irusskikh@marvell.com/ ==================== Signed-off-by:
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Igor Russkikh authored
On some adjacent code, fix bad code formatting Signed-off-by:
Ariel Elior <ariel.elior@marvell.com> Signed-off-by:
Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by:
Igor Russkikh <irusskikh@marvell.com> Signed-off-by:
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Igor Russkikh authored
MCP may signal driver about generic critical failure. Driver has to collect mdump information (get_retain), it pushes that to logs and triggers generic notification on "hardware attention" event. Signed-off-by:
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Igor Russkikh authored
Fan failure is sent by firmware, driver reacts on this error with newly introduced notification path. It will collect dump and shut down the device to prevent physical breakage Signed-off-by:
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Denis Bolotin authored
Upon tx timeout detection we do disable carrier and print TX queue info on TX timeout. We then raise hw error condition and trigger service task to handle this. This handler will capture extra debug info and then optionally trigger recovery procedure to try restore function. Signed-off-by:
Denis Bolotin <dbolotin@marvell.com> Signed-off-by:
Ariel Elior <aelior@marvell.com> Signed-off-by:
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Igor Russkikh authored
Driver has an ability to initiate a recovery process as a reaction to detected errors. But the codepath (recovery_process) was disabled and never active. Here we add ethtool private flag to allow user have the recovery procedure activated. We still do not enable this by default though, since in some configurations this is not desirable. E.g. this may impact other PFs/VFs. Signed-off-by:
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Igor Russkikh authored
On different hardware events we have to respond differently, on some of hardware indications hw attention (error condition) should be cleared by the driver to continue normal functioning. Here we introduce attention clear flags, and put them on some important events (in aeu_descs). Signed-off-by:
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Igor Russkikh authored
Thats probably a legacy code had double declaration of some fields. Cleanup this, removing copy and fixing references. Signed-off-by:
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Igor Russkikh authored
On various critical errors, notification handler should also report the err information into the management firmware. MFW can interact with server/motherboard backend agents - these are used by server manufacturers to monitor server HW health. Thus, it is important for driver to report on any faulty conditions Signed-off-by:
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Igor Russkikh authored
In a number of critical places not only debug trace should be printed, but the appropriate hw error condition should be raised and error handling/recovery should start. Introduce our new qed_hw_err_notify invocation in these places to record and indicate critical error conditions in hardware. Signed-off-by:
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Igor Russkikh authored
qede (ethernet level driver) registers a callback handler. This handler maintains eth dev state flags/bits to track error processing. It implements in place processing part for nonsleeping context (WARN_ON trigger), and a deferred (delayed work) part which triggers recovery process for recoverable errors. In later patches this atomic handler will come with more meat. We introduce err_flags on ethdevice structure, its being used to record error handling properties. Signed-off-by:
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Igor Russkikh authored
Here we introduce qed device error tracking flags and error types. qed_hw_err_notify is an entrace point to report errors. It'll notify higher level drivers (qede/qedr/etc) to handle and recover the error. List of posible errors comes from hardware interfaces, but could be extended in future. Signed-off-by:
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David S. Miller authored
Huazhong Tan says: ==================== net: hns3: add some cleanups for -next This patchset adds some cleanups for the HNS3 ethernet driver. ==================== Signed-off-by: -
Huazhong Tan authored
The skb_has_frag_list() in hns3_nic_net_xmit() is redundant, since skb_walk_frags() includes this checking implicitly. Reported-by:
Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by:
Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by:
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Huazhong Tan authored
There are some macros defined in hns3_enet.h, but not used in anywhere. Reported-by:
Yonglong Liu <liuyonglong@huawei.com> Signed-off-by:
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Huazhong Tan authored
When handling HCLGE_MBX_GET_LINK_STATUS, PF will return the link status to the VF, so the error log of hclge_get_link_info() is incorrect. Reported-by:
Jian Shen <shenjian15@huawei.com> Signed-off-by:
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Huazhong Tan authored
Since hclge_get_cfg() already has error print, so hclge_configure() should not print error when calling hclge_get_cfg() fail. Reported-by:
Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by:
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Huazhong Tan authored
This patch modifies some incorrect spelling. Reported-by:
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Thierry Reding authored
If a MAC address was passed via the device tree node for the r8152 device, use it and fall back to reading from EEPROM otherwise. This is useful for devices where the r8152 EEPROM was not programmed with a valid MAC address, or if users want to explicitly set a MAC address in the bootloader and pass that to the kernel. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Vlad Buslov authored
Flower tests used to create ingress filter with specified parent qdisc "parent ffff:" but dump them on "ingress". With recent commit that fixed tcm_parent handling in dump those are not considered same parent anymore, which causes iproute2 tc to emit additional "parent ffff:" in first line of filter dump output. The change in output causes filter match in tests to fail. Prevent parent qdisc output when dumping filters in flower tests by always correctly specifying "ingress" parent both when creating and dumping filters. Fixes: a7df4870 ("net_sched: fix tcm_parent in tc filter dump") Signed-off-by:
Vlad Buslov <vladbu@mellanox.com> Signed-off-by:
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- 13 May, 2020 18 commits
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DENG Qingfang authored
Currently, setting a bridge's self PVID to other value and deleting the default VID 1 renders untagged ports of that VLAN unable to talk to the CPU port: bridge vlan add dev br0 vid 2 pvid untagged self bridge vlan del dev br0 vid 1 self bridge vlan add dev sw0p0 vid 2 pvid untagged bridge vlan del dev sw0p0 vid 1 # br0 cannot send untagged frames out of sw0p0 anymore That is because the CPU port is set to security mode and its PVID is still 1, and untagged frames are dropped due to VLAN member violation. Set the CPU port to fallback mode so untagged frames can pass through. Fixes: 83163f7d ("net: dsa: mediatek: add VLAN support for MT7530") Signed-off-by:
DENG Qingfang <dqfext@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Daniel González Cabanelas authored
Some PHYs connected to this ethernet hardware support the WoL feature. But when WoL is enabled and the machine is powered off, the PHY remains waiting for a magic packet at max speed (i.e. 1Gbps), which is a waste of energy. Slow down the PHY speed before stopping the ethernet if WoL is enabled, and save some energy while the machine is powered off or sleeping. Tested using an Armada 370 based board (LS421DE) equipped with a Marvell 88E1518 PHY. Signed-off-by:
Daniel González Cabanelas <dgcbueu@gmail.com> Signed-off-by:
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Colin Ian King authored
Currently pointer table is being dereferenced on a null check of table->must_restore_filters before it is being null checked, leading to a potential null pointer dereference issue. Fix this by null checking table before dereferencing it when checking for a null table->must_restore_filters. Addresses-Coverity: ("Dereference before null check") Fixes: e4fe938c ("sfc: move 'must restore' flags out of ef10-specific nic_data") Signed-off-by:Colin Ian King <colin.king@canonical.com> Acked-by:
Edward Cree <ecree@solarflare.com> Signed-off-by:
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Michael Walle authored
The AR8031/AR8033 and the AR8035 support cable diagnostics. Adding driver support is straightforward, so lets add it. The PHY just do one pair at a time, so we have to start the test four times. The cable_test_get_status() can block and therefore we can just busy poll the test completion and continue with the next pair until we are done. The time delta counter seems to run at 125MHz which just gives us a resolution of about 82.4cm per tick. 100m cable, A/B/C/D open: Cable test started for device eth0. Cable test completed for device eth0. Pair: Pair A, result: Open Circuit Pair: Pair A, fault length: 107.94m Pair: Pair B, result: Open Circuit Pair: Pair B, fault length: 104.64m Pair: Pair C, result: Open Circuit Pair: Pair C, fault length: 105.47m Pair: Pair D, result: Open Circuit Pair: Pair D, fault length: 107.94m 1m cable, A/B connected, C shorted, D open: Cable test started for device eth0. Cable test completed for device eth0. Pair: Pair A, result: OK Pair: Pair B, result: OK Pair: Pair C, result: Short within Pair Pair: Pair C, fault length: 0.82m Pair: Pair D, result: Open Circuit Pair: Pair D, fault length: 0.82m Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
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Christoph Hellwig authored
While do_ipv6_getsockopt does not call the high-level recvmsg helper, the msghdr eventually ends up being passed to put_cmsg anyway, and thus needs msg_control_is_user set to the proper value. Fixes: 1f466e1f ("net: cleanly handle kernel vs user buffers for ->msg_control") Reported-by:
Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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David S. Miller authored
Michael Walle says: ==================== net: phy: broadcom: cable tester support Add cable tester support for the Broadcom PHYs. Support for it was developed on a BCM54140 Quad PHY which RDB register access. If there is a link partner the results are not as good as with an open cable. I guess we could retry if the measurement until all pairs had at least one valid result. changes since v1: - added Reviewed-by: tags - removed "div by 2" for cross shorts, just mention it in the commit message. The results are inconclusive if the tests are repeated. So just report the length as is for now. - fixed typo in commit message ==================== Signed-off-by: -
Michael Walle authored
Use the generic cable tester functions from bcm-phy-lib to add cable tester support. 100m cable, A/B/C/D open: Cable test started for device eth0. Cable test completed for device eth0. Pair: Pair A, result: Open Circuit Pair: Pair B, result: Open Circuit Pair: Pair C, result: Open Circuit Pair: Pair D, result: Open Circuit Pair: Pair A, fault length: 106.60m Pair: Pair B, fault length: 103.32m Pair: Pair C, fault length: 104.96m Pair: Pair D, fault length: 106.60m 1m cable, A/B connected, pair C shorted, D open: Cable test started for device eth0. Cable test completed for device eth0. Pair: Pair A, result: OK Pair: Pair B, result: OK Pair: Pair C, result: Short within Pair Pair: Pair D, result: Open Circuit Pair: Pair C, fault length: 0.82m Pair: Pair D, fault length: 1.64m 1m cable, A/B connected, pair C shorted with D: Cable test started for device eth0. Cable test completed for device eth0. Pair: Pair A, result: OK Pair: Pair B, result: OK Pair: Pair C, result: Short to another pair Pair: Pair D, result: Short to another pair Pair: Pair C, fault length: 1.64m Pair: Pair D, fault length: 1.64m The granularity of the length measurement seems to be 82cm. Signed-off-by:
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Michael Walle authored
Most modern broadcom PHYs support ECD (enhanced cable diagnostics). Add support for it in the bcm-phy-lib so they can easily be used in the PHY driver. There are two access methods for ECD: legacy by expansion registers and via the new RDB registers which are exclusive. Provide functions in two variants where the PHY driver can choose from. To keep things simple for now, we just switch the register access to expansion registers in the RDB variant for now. On the flipside, we have to keep a bus lock to prevent any other non-legacy access on the PHY. The results of the intra-pair tests are inconclusive (at least for the BCM54140). Most of the times half the length is reported but sometimes the length is correct. Signed-off-by:
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Michael Walle authored
Add the convenience function to do a read-modify-write. This has the additional benefit of saving one write to the selection register. Signed-off-by:
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Michael Walle authored
Add helper to read and write expansion registers without taking the mdio lock. Please note, that this changes the semantics of the read and write. Before there was no lock between selecting the expansion register and the actual read/write. This may lead to access failures if there are parallel accesses. Instead take the bus lock during the whole access cycle. Signed-off-by:
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Oleksij Rempel authored
Add initial cable testing support. This PHY needs only 100usec for this test and it is recommended to run it before the link is up. For now, provide at least ethtool support, so it can be tested by more developers. This patch was tested with TJA1102 PHY with following results: - No cable, is detected as open - 1m cable, with no connected other end and detected as open - a 40m cable (out of spec, max lenght should be 15m) is detected as OK. Current patch do not provide polarity test support. This test would indicate not proper wire connection, where "+" wire of main phy is connected to the "-" wire of the link partner. Signed-off-by:
Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by:
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Christoph Hellwig authored
The code had historically been ignoring these errors, and my recent refactoring changed that, which broke ssh in some setups. Fixes: 2618d530 ("net/scm: cleanup scm_detach_fds") Reported-by:
Ido Schimmel <idosch@idosch.org> Signed-off-by:
Ido Schimmel <idosch@mellanox.com> Tested-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by:
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David S. Miller authored
Martin Blumenstingl says: ==================== dwmac-meson8b Ethernet RX delay configuration The Ethernet TX performance has been historically bad on Meson8b and Meson8m2 SoCs because high packet loss was seen. I found out that this was related (yet again) to the RGMII TX delay configuration. In the process of discussing the big picture (and not just a single patch) [0] with Andrew I discovered that the IP block behind the dwmac-meson8b driver actually seems to support the configuration of the RGMII RX delay (at least on the Meson8b SoC generation). Since I sent the first RFC I got additional documentation from Jianxin (many thanks!). Also I have discovered some more interesting details: - Meson8b Odroid-C1 requires an RX delay (by either the PHY or the MAC) Based on the vendor u-boot code (not upstream) I assume that it will be the same for all Meson8b and Meson8m2 boards - Khadas VIM2 seems to have the RX delay built into the PCB trace length. When I enable the RX delay on the PHY or MAC I can't get any data through. I expect that we will have the same situation on all GXBB, GXM, AXG, G12A, G12B and SM1 boards. Further clarification is needed here though (since I can't visually see these lengthened traces on the PCB). This will be done before sending patches for these boards. Dependencies for this series: There is a soft dependency for patch #2 on commit f2253143 "dt-bindings: net: dwmac: increase 'maxItems' for 'clocks', 'clock-names' properties" which is currently in Rob's -next tree. That commit is needed to make the dt-bindings schema validation pass for patch #2. That patch has been for ~4 weeks in Robs tree, so I assume that is not going to be dropped. Changes since RFC v2 at [2]: - dropped $ref: /schemas/types.yaml#definitions/uint32 from the "amlogic,rx-delay-ns" in patch #1 ("Don't need to define the type when in standard units." says Rob - thanks, I learned something new). Also use "default: 0" for for this property instead of explaining it in the description text. - added a note to the cover-letter about a hidden dependency for dt-binding schema validation in patch #2 - Added Andrew's Reviewed-by to patches 1-7. Thank you again for the quick and detailed reviews, I appreciate this! - error out if the (optional) timing-adjustment clock is missing but we're asked to enable the RGMII RX delay. The MAC won't work in this specific case and either the RX delay has to be provided by the PHY or the timing-adjustment clock has to be added. - dropped the dts patches (#9-11) which were only added to give an overview how this is going to be used. those will be sent separately - dropped the RFC prefix Changes since RFC v1 at [1]: - add support for the timing adjustment clock input (dt-bindings and in the driver) thanks to the input from the unnamed Ethernet engineer at Amlogic. This is the missing link between the fclk_div2 clock and the Ethernet controller on Meson8b (no traffic would flow if that clock was disabled) - add support fot the amlogic,rx-delay-ns property. The only supported values so far are 0ns and 2ns. The registers seem to allow more precise timing adjustments, but I could not make that work so far. - add more register documentation (for the new RX delay bits) and unified the placement of existing register documentation. Again, thanks to Jianxin and the unnamed Ethernet engineer at Amlogic - DO NOT MERGE: .dts patches to show the conversion of the Meson8b and Meson8m2 boards to "rgmii-id". I didn't have time for all arm64 patches yet, but these will switch to phy-mode = "rgmii-txid" with amlogic,rx-delay-ns = <0> (because the delay seems to be provided by the PCB trace length). [0] https://patchwork.kernel.org/patch/11309891/ [1] https://patchwork.kernel.org/cover/11310719/ [2] https://patchwork.kernel.org/cover/11518257/ ==================== Signed-off-by:
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Martin Blumenstingl authored
Configure the PRG_ETH0_ADJ_* bits to enable or disable the RX delay based on the various RGMII PHY modes. For now the only supported RX delay settings are: - disabled, use for example for phy-mode "rgmii-id" - 0ns - this is treated identical to "disabled", used for example on boards where the PHY provides 2ns TX delay and the PCB trace length already adds 2ns RX delay - 2ns - for whenever the PHY cannot add the RX delay and the traces on the PCB don't add any RX delay Disabling the RX delay (in case u-boot enables it, which is the case for example on Meson8b Odroid-C1) simply means that PRG_ETH0_ADJ_ENABLE, PRG_ETH0_ADJ_SETUP, PRG_ETH0_ADJ_DELAY and PRG_ETH0_ADJ_SKEW should be disabled (just disabling PRG_ETH0_ADJ_ENABLE may be enough, since that disables the whole re-timing logic - but I find it makes more sense to clear the other bits as well since they depend on that setting). u-boot on Odroid-C1 uses the following steps to enable a 2ns RX delay: - enabling enabling the timing adjustment clock - enabling the timing adjustment logic by setting PRG_ETH0_ADJ_ENABLE - setting the PRG_ETH0_ADJ_SETUP bit The documentation for the PRG_ETH0_ADJ_DELAY and PRG_ETH0_ADJ_SKEW registers indicates that we can even set different RX delays. However, I could not find out how this works exactly, so for now we only support a 2ns RX delay using the exact same way that Odroid-C1's u-boot does. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Martin Blumenstingl authored
The timing adjustment clock will need similar logic as the RGMII clock: It has to be enabled in the driver conditionally and when the driver is unloaded it should be disabled again. Extract the existing code for the RGMII clock into a new function so it can be re-used. Reviewed-by:
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Martin Blumenstingl authored
The PRG_ETHERNET registers have a built-in timing adjustment circuit which can provide the RX delay in RGMII mode. This is driven by an external (to this IP, but internal to the SoC) clock input. Fetch this clock as optional (even though it's there on all supported SoCs) since we just learned about it and existing .dtbs don't specify it. Reviewed-by:
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Martin Blumenstingl authored
The PRG_ETH0_ADJ_* are used for applying the RGMII RX delay. The public datasheets only have very limited description for these registers, but Jianxin Pan provided more detailed documentation from an (unnamed) Amlogic engineer. Add the PRG_ETH0_ADJ_* bits along with the improved description. Suggested-by:
Jianxin Pan <jianxin.pan@amlogic.com> Reviewed-by:
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Martin Blumenstingl authored
Move the documentation for the TX delay above the PRG_ETH0_TXDLY_MASK definition. Future commits will add more registers also with documentation above their register bit definitions. Move the existing comment so it will be consistent with the upcoming changes. Reviewed-by:
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