- 13 Feb, 2018 14 commits
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Tvrtko Ursulin authored
We can implement limited RC6 counter wrap-around protection under the assumption that clients will be reading this value more frequently than the wrap period on a given platform. With the typical wrap-around period being ~90 minutes, even with the exception of Baytrail which wraps every 13 seconds, this sounds like a reasonable assumption. Implementation works by storing a 64-bit software copy of a hardware RC6 counter, along with the previous HW counter snapshot. This enables it to detect wrap is polled frequently enough and keep the software copy monotonically incrementing. v2: * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and indexing. * Fixed off-by-one in wrap-around handling. (Chris Wilson) v3: * Simplify index checking by using unsigned int. (Chris Wilson) * Expand the comment to explain why indexing works. v4: * Use __int128 if supported. v5: * Use mul_u64_u32_div. (Chris Wilson) Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852 Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180208160036.29919-1-tvrtko.ursulin@linux.intel.comAcked-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
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Tvrtko Ursulin authored
Header uses I915_NUM_ENGINES so needs to include i915.gem.h, and also it uses requests so we can forward declare struct drm_i915_gem_request. Signed-off-by:
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Jani Nikula authored
Cleanup similar to INTEL_PCH_TYPE(). No functional changes. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/798893c24728a1c766cb21c57ae0943e5859c897.1517851783.git.jani.nikula@intel.com
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Jani Nikula authored
Simplify intel_virt_detect_pch() by making it return a PCH id rather than returning the PCH type and setting PCH id for some PCHs. Map the PCH id to PCH type using the shared routine. This gives us sanity check on the supported combinations also in the virtualized setting. Reviewed-by:
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Jani Nikula authored
Make the code slightly more pleasant to look at. No functional changes. Reviewed-by:
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Jani Nikula authored
Make the logic in intel_detect_pch() easier to follow, and make the PCH id to type mapping reusable. No functional changes. Reviewed-by:
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Chris Wilson authored
igt_partial_tiling managed to fail with an -EBUSY. This usually means a pin leak, but that should be impossible given the test setup. Add a couple of error messages to help identify the path that failed. References: https://bugs.freedesktop.org/show_bug.cgi?id=105073Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180213120940.21579-1-chris@chris-wilson.co.uk
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Mahesh Kumar authored
This patch program default values of MBus credit during pipe enable. Changes Since V1: - Add WARN_ON (Paulo) - Remove TODO comment - Program 0 during pipe disable - Rebase Changes since V2: - We don't need to do anything when disabling the pipe Changes since V3 (from Paulo): - Remove WARN() that we'll never be able to trigger (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
James Ausmus <james.ausmus@intel.com> Signed-off-by:
Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by:
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Mahesh Kumar authored
This patch initializes MBus during display initialization. Changes since V2 (from Paulo): - Don't forget to remove the WARN_ON(1) call. Changes since V1: - Rebase to use function like Macros Reviewed-by:
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Mahesh Kumar authored
ICL has 2 slices of DBuf, enable both the slices during display init. Ideally we should only enable the second slice when needed in order to save power, but while we're not there yet, adopt the simpler solution to keep us bug-free. v2 (from Paulo): - Add the TODO comment. - Reorganize where things are defined. - Fix indentation. - Remove unnecessary POSTING_READ() calls. - Improve the commit message. Reviewed-by:
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Paulo Zanoni authored
This code is similar enough to the CNL code that I considered just adding ICL support to the CNL function, but I think it's still different enough, and having a function specific to ICL allows us to more easily adapt code in case the spec changes more later. We're still missing the power wells and the mbus code, so leave those pieces with a FIXME comment while they're not here yet. v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits. v3: Use _MMIO_PORT() (Ville). Reviewed-by: James Ausmus <james.ausmus@intel.com> (v2) Signed-off-by:
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Paulo Zanoni authored
This commit adds the basic CDCLK functions, but it's still missing pieces of the display initialization sequence. v2: - Implement the voltage levels. - Rebase. v3: - Adjust to the new "bypass" clock (Imre). - Call intel_dump_cdclk_state() too. - Rename a variable to avoid confusion. - Simplify the DVFS part. v4: - Remove wrong bit definition (James). - Also drive-by fix the coding style for the register definition we touched. v5: - Comment style (checkpatch). Cc: James Ausmus <james.ausmus@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by:
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Paulo Zanoni authored
On ICL we have two sets of registers: one for port A and another for port B. The set of port A registers is the same as the CNL registers. Since the procmon table on ICL is the same we want to reuse the CNL function. To do that we add a port argument and make CNL always call the function passing port A. This way, we'll be able to easily reuse the function on ICL when we add icl_display_core_init(). v2: Don't use _PICK() when you can use a ternary operator. v3: Don't use a ternary operation when you can use _MMIO_PORT (Ville). Add an extra comment about why we're passing PORT_A (James). Reviewed-by: -
David Weinehall authored
While the comment singles out Port A or B, the code says Port A or *D*. Looking at the history it seems that the comment was added after the code, so it seems likely that the code is correct, not the comment. CC: Jani Nikula <jani.nikula@intel.com> CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Reviewed-by:
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- 12 Feb, 2018 5 commits
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Chris Wilson authored
When initialising the page directories, we set the GTT entries and the tree to the scratch page. We have already replaced the DMA fill with memset64(), but we can similarly use memset_p() to set the pointer array. References: 4dd504f7 ("drm/i915: Use memset64() to prefill the GTT page") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
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Imre Deak authored
On BXT/GLK GEN6_PCODE_READ_RC6VIDS fails with MAILBOX_P24C_CC_ILLEGAL_CMD, so don't try to do the query on these platforms. Do it only on SNB, IVB and HSW, where we use this command anyway for RC6 enabling. Based on my tests the command also succeeds on all LLC platforms, but it's not clear if it's really supported on those (it returns 0 aka 245mv for all RC6 states everywhere except on SNB). BSpec lists the command as supported on SKL+ (see P24C_PCODE_MAILBOX_INTERFACE) but that's clearly incorrect, since on SKL/KBL the same command ID is used for SKL_PCODE_LOAD_HDCP_KEYS. Since the command fails on BXT/GLK, the BSpec command list is also incorrect for those platforms (see P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR). I filed a request to update that info in Bspec, but for now let's assume a minimal set of platforms where the command is supported. References: https://bugs.freedesktop.org/show_bug.cgi?id=103337Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Chris Wilson authored
When dumping the engine, we print out the current register values. This requires the rpm wakeref. If the device is alseep, we can assume the engine is asleep (and the register state is uninteresting) so skip and only acquire the rpm wakeref if the device is already awake. Reported-by:
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Chris Wilson authored
If the entire device is powered off, we can safely assume that the engine is also asleep (and idle). Reported-by:
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Chris Wilson authored
If we fail to reset the GPU (i915_reset()), we do one final intel_gpu_reset() attempt as we mark the device wedged. The idea here is even though the GPU has proven unreliable (and so we want to stop using it for the time being), we don't want it spinning away in the background whilst the driver idles so we try to reset it one more time. However, we want to dump the i915_gem_set_wedged() debugging info before we do, so that we can see the accurate state of the GPU when it failed. Signed-off-by:
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- 09 Feb, 2018 5 commits
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Tvrtko Ursulin authored
Instead of INTEL_GEN != x use !IS_GENx for more optimisation opportunities. Signed-off-by:
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Tvrtko Ursulin authored
Coccinelle patch: @@ identifier p; @@ -INTEL_INFO(p)->gen +INTEL_GEN(p) Signed-off-by:
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Ville Syrjälä authored
Most of our ioctl functions have an _ioctl suffix in the name. I like that idea since it makes it easy to figure out how the function is going to get called. Rename the handful of exceptions to follow the same pattern. Signed-off-by:
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Ville Syrjälä authored
Check that userspace isn't passing in garbage in the colorkey ioctl flags. Signed-off-by:
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Imre Deak authored
FORCEWAKE_ACK is depricated by BSpec at least starting from BDW, referring to the multi-threaded version of it instead. Accessing FORCEWAKE_ACK triggers an unclaimed register access error - at least on GLK - see the Reference: below. The correct registers to use would be FORCEWAKE_MT_ACK on IVB+ and FORCEWAKE_ACK_RENDER_GEN9 on SKL+ like it's done elsewhere in the driver. The forcewake check itself is inconsistent and redundant, since there could be other forcewake requesters besides the kernel (being the multithreaded version of the register) and the kernel's per-domain forcewake counters are shown anyway at the end of the file. So let's just remove the check. Suggested-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
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- 08 Feb, 2018 16 commits
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Chris Wilson authored
Since commit 4a118ecb ("drm/i915: Filter out spurious execlists context-switch interrupts") we probe execlists->active, and no longer have to peek at the execlist interrupt to determine if the tasklet still needs to be run to drain the ELSP. References: 4a118ecb ("drm/i915: Filter out spurious execlists context-switch interrupts") Signed-off-by:
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Chris Wilson authored
clang is confused by our if-else-chain that abruptly exits before a final else: drivers/gpu/drm/i915/intel_crt.c:821:11: warning: variable 'status' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (ret < 0) ^~~~~~~ drivers/gpu/drm/i915/intel_crt.c:826:9: note: uninitialized use occurs here return status; ^~~~~~ drivers/gpu/drm/i915/intel_crt.c:821:7: note: remove the 'if' if its condition is always true else if (ret < 0) ^~~~~~~~~~~~ drivers/gpu/drm/i915/intel_crt.c:761:12: note: initialize the variable 'status' to silence this warning int status, ret; In this case, we can reduce the final else-if clause to an unconditional else. Signed-off-by: -
Chris Wilson authored
The struct platform_device memdups the provided data pointer requiring us to free the template we construct during lpe_audio_platdev_create(): unreferenced object 0xffff88026eafe400 (size 512): comm "insmod", pid 6850, jiffies 4295060179 (age 22.300s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<000000008e4a834c>] intel_audio_init+0x9/0x30 [i915] [<000000001360e195>] i915_driver_load+0x802/0x14e0 [i915] [<00000000ab3f0e99>] i915_pci_probe+0x29/0x70 [i915] [<0000000016330ee5>] pci_device_probe+0x9c/0x120 [<000000000257d054>] driver_probe_device+0x307/0x470 [<000000009f0a6cb6>] __driver_attach+0x98/0xe0 [<0000000031b46e58>] bus_for_each_dev+0x57/0x80 [<000000000e28239d>] bus_add_driver+0x1bd/0x260 [<00000000abbe5161>] driver_register+0x52/0xc0 [<000000005c6e23d4>] do_one_initcall+0x36/0x150 [<00000000a55002f4>] do_init_module+0x56/0x1d7 [<00000000e48f2217>] load_module+0x23c8/0x2910 [<000000002b60bf61>] SyS_finit_module+0xb8/0xd0 [<0000000041cbad96>] entry_SYSCALL_64_fastpath+0x17/0x70 [<000000009f1d37ab>] 0xffffffffffffffff Signed-off-by: -
Chris Wilson authored
The unused-but-set warning enabled by W=1 catches out a lot of the atomic helper iterator macros and drown us in their noise (or trip over Werror and die). Path of least resistance is to ignore the warning. Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Chris Wilson authored
drivers/gpu/drm/i915/i915_gem_internal.c:183: warning: No description found for parameter 'i915' drivers/gpu/drm/i915/i915_gem_internal.c:183: warning: No description found for parameter 'size' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/i915_gem_execbuffer.c:1983: warning: No description found for parameter 'dev_priv' drivers/gpu/drm/i915/i915_gem_execbuffer.c:1983: warning: No description found for parameter 'file' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/i915_syncmap.c:92: warning: No description found for parameter 'root' drivers/gpu/drm/i915/i915_syncmap.c:155: warning: No description found for parameter 'root' drivers/gpu/drm/i915/i915_syncmap.c:155: warning: No description found for parameter 'id' drivers/gpu/drm/i915/i915_syncmap.c:155: warning: No description found for parameter 'seqno' drivers/gpu/drm/i915/i915_syncmap.c:354: warning: No description found for parameter 'root' drivers/gpu/drm/i915/i915_syncmap.c:354: warning: No description found for parameter 'id' drivers/gpu/drm/i915/i915_syncmap.c:354: warning: No description found for parameter 'seqno' drivers/gpu/drm/i915/i915_syncmap.c:396: warning: No description found for parameter 'root' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/i915_drv.c:891: warning: No description found for parameter 'ent' Signed-off-by:
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Chris Wilson authored
The comment is very old and quite misleading now. drivers/gpu/drm/i915/i915_gem_context.c:349: warning: No description found for parameter 'dev_priv' drivers/gpu/drm/i915/i915_gem_context.c:349: warning: No description found for parameter 'file_priv' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/i915_gem_request.c:941: warning: No description found for parameter 'write' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/i915_gem_userptr.c:761: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_gem_userptr.c:761: warning: No description found for parameter 'data' drivers/gpu/drm/i915/i915_gem_userptr.c:761: warning: No description found for parameter 'file' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/intel_ringbuffer.c:179: warning: No description found for parameter 'req' drivers/gpu/drm/i915/intel_ringbuffer.c:741: warning: No description found for parameter 'req' drivers/gpu/drm/i915/intel_ringbuffer.c:741: warning: No description found for parameter 'cs' Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/i915_gpu_error.c:1815: warning: No description found for parameter 'dev_priv' drivers/gpu/drm/i915/i915_gpu_error.c:1815: warning: No description found for parameter 'engine_mask' drivers/gpu/drm/i915/i915_gpu_error.c:1815: warning: No description found for parameter 'error_msg' drivers/gpu/drm/i915/i915_gpu_error.c:1815: warning: Excess function parameter 'dev' description in 'i915_capture_error_state' Signed-off-by:
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Chris Wilson authored
After we assert the reset request (and wait for 20us), when the device has been fully reset it asserts the reset-status bit. Before we stop requesting the reset and allow the device to return to normal, we should wait for the reset to be completed. (Similar to how we wait for the device to return to normal after deasserting the reset request.) v2: Rename i915_reset_completed() probe to not cause as much confusion. Signed-off-by:
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Chris Wilson authored
Although the mmio are uncached and so should be flushed on every write, be paranoid and do a mmio read after setting the ring head/tail to be sure they have taken effect before moving on. v2: post tail to be pleasing to the eye Signed-off-by:
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Chris Wilson authored
Reduce the window of opportunity for set-wedged being called concurrently with reset (after i915_reset() has performed the i915_gem_unset_wedged()) by moving the set_bit(I915_WEDGED) to before we complete the inflight requests. When i915_reset() is being blocked on a request, such completion may allow it to start and beginning resetting the GPU before i915_gem_set_wedged() has finished (and so before set-wedge will have marked the device as wedged). As such, i915_gem_init_hw() may see a wedged device even from inside i915_reset(). References: 36703e79 ("drm/i915: Break modeset deadlocks on reset") Signed-off-by:
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